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Paper Abstract and Keywords
Presentation 2010-01-28 15:25
Suppression of Power-supply-voltage Fluctuation on System LSIs using Power Gating technique
Ken-ichi Kawasaki, Koichi Nakayama, Satoshi Tanabe, Hisanori Fujisawa (Fujitsu Lab.) CAS2009-69
Abstract (in Japanese) (See Japanese page) 
(in English) A power gating technique minimizing the area overhead of power switches was developed for low power SOCs.
The amount of essential power switches to deliver power supply to a circuit is preliminarily divided to plural cluster of power switches. The appropriate values including the amount of power switches and the time turning on power switches in each cluster are determined using this technique to suppress the power-supply-voltage fluctuation when power switches are turned on.
We applied this technique to a trial LSI fabricated in 65-nm CMOS technology and measured the actual power-supply-voltage fluctuation. When the power switches on the 2.7 million gate scale circuit were turned on, the fluctuation was suppressed to less than 2mV even without additional power switches.
Keyword (in Japanese) (See Japanese page) 
(in English) Power Gating / Leakage Current / Power Switch / Rush Current / / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 396, CAS2009-69, pp. 31-36, Jan. 2010.
Paper # CAS2009-69 
Date of Issue 2010-01-21 (CAS) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CAS2009-69

Conference Information
Committee CAS  
Conference Date 2010-01-28 - 2010-01-29 
Place (in Japanese) (See Japanese page) 
Place (in English) Kyoudai-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To CAS 
Conference Code 2010-01-CAS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Suppression of Power-supply-voltage Fluctuation on System LSIs using Power Gating technique 
Sub Title (in English)  
Keyword(1) Power Gating  
Keyword(2) Leakage Current  
Keyword(3) Power Switch  
Keyword(4) Rush Current  
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1st Author's Name Ken-ichi Kawasaki  
1st Author's Affiliation Fujitsu Laboratories (Fujitsu Lab.)
2nd Author's Name Koichi Nakayama  
2nd Author's Affiliation Fujitsu Laboratories (Fujitsu Lab.)
3rd Author's Name Satoshi Tanabe  
3rd Author's Affiliation Fujitsu Laboratories (Fujitsu Lab.)
4th Author's Name Hisanori Fujisawa  
4th Author's Affiliation Fujitsu Laboratories (Fujitsu Lab.)
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Speaker Author-1 
Date Time 2010-01-28 15:25:00 
Presentation Time 25 minutes 
Registration for CAS 
Paper # CAS2009-69 
Volume (vol) vol.109 
Number (no) no.396 
Page pp.31-36 
#Pages 6 
Date of Issue 2010-01-21 (CAS) 

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