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Paper Abstract and Keywords
Presentation 2010-02-05 14:30
Performance of Cu Dual-Damascene Interconnects Using a Thin Ti-Based Self-Formed Barrier Layer for 28-nm Node and Beyond
K. Ohmori, K. Mori, K. Maekawa (Renesas), Kazuyuki Kohama, Kazuhiro Ito (Kyoto Univ.), T. Ohnishi, M. Mizuno (KOBE STEEL), K. Asai (Renesas), M. Murakami (Ritsumeikan Trust), Hiroshi Miyatake (Renesas) SDM2009-188
Abstract (in Japanese) (See Japanese page) 
(in English) With continuous shrinkage of advanced ULSIs, the impact of line resistance on the devices has become more and more serious. In order to achieve low resistance and high reliability of Cu interconnects, we applied a thin Ti-based self-formed barrier layer using Cu-Ti alloy seed to 45nm-node dual-damascene interconnects and evaluated its performance. The microstructure analysis by transmission electron microscope and energy dispersive X-ray fluorescence spectrometer has revealed that 2nm-thick Ti-based barrier layer is self-formed at the interface between Cu and low-k dielectrics. The line resistance and via resistance decrease significantly, compared with those of conventional Ta/TaN barrier system. The stress induced voiding performance is also drastically improved using self-formed barrier process. These results suggest Ti-based self-formed barrier process is one of the most promising candidates for advanced Cu interconnects.
Keyword (in Japanese) (See Japanese page) 
(in English) Cu line / CuTi / self-formed barrier / / / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 412, SDM2009-188, pp. 37-41, Feb. 2010.
Paper # SDM2009-188 
Date of Issue 2010-01-29 (SDM) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee SDM  
Conference Date 2010-02-05 - 2010-02-05 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To SDM 
Conference Code 2010-02-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Performance of Cu Dual-Damascene Interconnects Using a Thin Ti-Based Self-Formed Barrier Layer for 28-nm Node and Beyond 
Sub Title (in English)  
Keyword(1) Cu line  
Keyword(2) CuTi  
Keyword(3) self-formed barrier  
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1st Author's Name K. Ohmori  
1st Author's Affiliation Renesas Technology Corp. (Renesas)
2nd Author's Name K. Mori  
2nd Author's Affiliation Renesas Technology Corp. (Renesas)
3rd Author's Name K. Maekawa  
3rd Author's Affiliation Renesas Technology Corp. (Renesas)
4th Author's Name Kazuyuki Kohama  
4th Author's Affiliation Kyoto University (Kyoto Univ.)
5th Author's Name Kazuhiro Ito  
5th Author's Affiliation Kyoto University (Kyoto Univ.)
6th Author's Name T. Ohnishi  
6th Author's Affiliation KOBE STEEL, LTD (KOBE STEEL)
7th Author's Name M. Mizuno  
7th Author's Affiliation KOBE STEEL, LTD (KOBE STEEL)
8th Author's Name K. Asai  
8th Author's Affiliation Renesas Technology Corp. (Renesas)
9th Author's Name M. Murakami  
9th Author's Affiliation The Ritsumeikan Trust (Ritsumeikan Trust)
10th Author's Name Hiroshi Miyatake  
10th Author's Affiliation Renesas Technology Corp. (Renesas)
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Speaker Author-1 
Date Time 2010-02-05 14:30:00 
Presentation Time 30 minutes 
Registration for SDM 
Paper # SDM2009-188 
Volume (vol) vol.109 
Number (no) no.412 
Page pp.37-41 
#Pages 5 
Date of Issue 2010-01-29 (SDM) 

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