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| Presentation | 2010-02-05 15:15 Chip-Level and Package-Level Seamless Interconnect Technologies for Advanced Packaging Shintaro Yamamichi, Kentaro Mori, Katsumi Kikuchi, Hideya Murai, D. Ohshima, Y. Nakashima (NEC), Kouji Soejima, Masaya Kawano (NEC Electronics), Tomoo Murakami (NEC)  SDM2009-189 Link to ES Tech. Rep. Archives: SDM2009-189 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Interposer-process-oriented thick-Cu-wiring technologies have been developed. Cu wiring thickness is 5 to 10 um, and interlayer dielectric is organic resin. Chip-level seamless interconnects are realized using a resin CMP process, and reliability on a flip-chip ball grid array (FCBGA) package is confirmed with these interconnects. Package-level seamless interconnects are formed by embedding a thinned CPU chip into a resin on Cu base plate. This seamless package is thinner, and has lower thermal resistance and better power delivery, compared to a conventional FCBGA package. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Seamless / Multi-layer wiring / Superconnect / Embedded active / Interposer / Packaging / / | |
| Reference Info. | IEICE Tech. Rep., vol. 109, no. 412, SDM2009-189, pp. 43-48, Feb. 2010. | |
| Paper # | SDM2009-189 | |
| Date of Issue | 2010-01-29 (SDM) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | SDM2009-189 Link to ES Tech. Rep. Archives: SDM2009-189 |
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| Conference Information | |
| Committee | SDM |
| Conference Date | 2010-02-05 - 2010-02-05 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | SDM |
| Conference Code | 2010-02-SDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Chip-Level and Package-Level Seamless Interconnect Technologies for Advanced Packaging |
| Sub Title (in English) | |
| Keyword(1) | Seamless |
| Keyword(2) | Multi-layer wiring |
| Keyword(3) | Superconnect |
| Keyword(4) | Embedded active |
| Keyword(5) | Interposer |
| Keyword(6) | Packaging |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Shintaro Yamamichi |
| 1st Author's Affiliation | NEC Corporation (NEC) |
| 2nd Author's Name | Kentaro Mori |
| 2nd Author's Affiliation | NEC Corporation (NEC) |
| 3rd Author's Name | Katsumi Kikuchi |
| 3rd Author's Affiliation | NEC Corporation (NEC) |
| 4th Author's Name | Hideya Murai |
| 4th Author's Affiliation | NEC Corporation (NEC) |
| 5th Author's Name | D. Ohshima |
| 5th Author's Affiliation | NEC Corporation (NEC) |
| 6th Author's Name | Y. Nakashima |
| 6th Author's Affiliation | NEC Corporation (NEC) |
| 7th Author's Name | Kouji Soejima |
| 7th Author's Affiliation | NEC Electronics Corporation (NEC Electronics) |
| 8th Author's Name | Masaya Kawano |
| 8th Author's Affiliation | NEC Electronics Corporation (NEC Electronics) |
| 9th Author's Name | Tomoo Murakami |
| 9th Author's Affiliation | NEC Corporation (NEC) |
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| Speaker | Author-1 |
| Date Time | 2010-02-05 15:15:00 |
| Presentation Time | 30 minutes |
| Registration for | SDM |
| Paper # | SDM2009-189 |
| Volume (vol) | vol.109 |
| Number (no) | no.412 |
| Page | pp.43-48 |
| #Pages | 6 |
| Date of Issue | 2010-01-29 (SDM) |
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