Paper Abstract and Keywords |
Presentation |
2010-03-02 13:45
[Poster Presentation]
Automatic Code Parallelization base on quantitative evaluation of data transfer for multi-layered cache architecture Takuya Noritake, Nobuhiko Sugino (Tokyo Inst. of Tech.) CAS2009-119 SIP2009-164 CS2009-114 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
An automatic code parallelization method based on quantitative evaluation of data transfer for multi-layered cache architecture is proposed. In order to effectively exploit burst transmission scheme at cache units, a procedure to pack data of higher temporal and spatial locality is given. Then, data packages and the corresponding instructions are assigned onto caches and processor cores, respectively, according to evaluation in data dependency, data transmission duration and cache capacity. Finally, preload operations for caches are scheduled at appropriate timing, so that bus conflicts and redundant data transmissions are avoided. The experimental results conducted for several example programs show effectiveness of the proposed method. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Multi-core / Multi-layer cache / Scheduling / Automatic parallelization / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 109, no. 434, CAS2009-119, pp. 235-236, March 2010. |
Paper # |
CAS2009-119 |
Date of Issue |
2010-02-22 (CAS, SIP, CS) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CAS2009-119 SIP2009-164 CS2009-114 |
Conference Information |
Committee |
SIP CAS CS |
Conference Date |
2010-03-01 - 2010-03-02 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Hotel Breeze Bay Marina, Miyakojima |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Signal processing for networking and communications, and others |
Paper Information |
Registration To |
CAS |
Conference Code |
2010-03-SIP-CAS-CS |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Automatic Code Parallelization base on quantitative evaluation of data transfer for multi-layered cache architecture |
Sub Title (in English) |
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Multi-core |
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Multi-layer cache |
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Scheduling |
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Automatic parallelization |
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1st Author's Name |
Takuya Noritake |
1st Author's Affiliation |
Tokyo Institute of Technorogy (Tokyo Inst. of Tech.) |
2nd Author's Name |
Nobuhiko Sugino |
2nd Author's Affiliation |
Tokyo Institute of Technorogy (Tokyo Inst. of Tech.) |
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Speaker |
Author-1 |
Date Time |
2010-03-02 13:45:00 |
Presentation Time |
60 minutes |
Registration for |
CAS |
Paper # |
CAS2009-119, SIP2009-164, CS2009-114 |
Volume (vol) |
vol.109 |
Number (no) |
no.434(CAS), no.435(SIP), no.436(CS) |
Page |
pp.235-236 |
#Pages |
2 |
Date of Issue |
2010-02-22 (CAS, SIP, CS) |
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