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Paper Abstract and Keywords
Presentation 2010-03-12 10:50
High-Level Design Conditions for Post-Fabrication Timing-Adjustable Datapaths
Akira Tehara, Mineo Kaneko (JAIST) VLD2009-122
Abstract (in Japanese) (See Japanese page) 
(in English) With the progress of fabrication-process technology, the variation of signal transmission delay due to
variations in process parameters becomes larger, and the yield degradation due to timing errors becomes a serious
problem. Conventionally, the problem has been fixed by introducing a timing-margin, but it often degrades the
circuit performance too much with an excess timing-margin. To overcome this problem, intentional clock skew
for avoiding timing error is one of promising techniques. In this paper, we discuss a datapath which has a good
performance in skew adjustability, that is, such datapath for which the skew adjustment succeeds at a higher rate.
Since the skew adjustment fails when a skew constraint graph includes positive cycles, we propose a novel resource
assignment which suppresses potential positive cycles in the skew constraint graph. The effectiveness of this resource
assignment is evaluated by the improvement of the success rate through Monte Carlo Simulation.
Keyword (in Japanese) (See Japanese page) 
(in English) timing-adjustability / datapath / skew / functional unit assignment / / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 462, VLD2009-122, pp. 139-144, March 2010.
Paper # VLD2009-122 
Date of Issue 2010-03-03 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2009-122

Conference Information
Committee VLD  
Conference Date 2010-03-10 - 2010-03-12 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for System-on-Silicon 
Paper Information
Registration To VLD 
Conference Code 2010-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) High-Level Design Conditions for Post-Fabrication Timing-Adjustable Datapaths 
Sub Title (in English)  
Keyword(1) timing-adjustability  
Keyword(2) datapath  
Keyword(3) skew  
Keyword(4) functional unit assignment  
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1st Author's Name Akira Tehara  
1st Author's Affiliation Japan Adavanced Institute of Science and Thechnology (JAIST)
2nd Author's Name Mineo Kaneko  
2nd Author's Affiliation Japan Adavanced Institute of Science and Thechnology (JAIST)
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Speaker Author-1 
Date Time 2010-03-12 10:50:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2009-122 
Volume (vol) vol.109 
Number (no) no.462 
Page pp.139-144 
#Pages 6 
Date of Issue 2010-03-03 (VLD) 

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