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Paper Abstract and Keywords
Presentation 2010-03-12 13:55
An Acceleration of Soft Error Torelance Estimation Method for Sequential Circuits by Reducing the Number of States
Yusuke Akamine, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.) VLD2009-126
Abstract (in Japanese) (See Japanese page) 
(in English) Soft error tolerance estimation method is necessary for the soft error aware logic design. We proposed an estimation method with Markov model for sequential circuits, which can analyze the behavior of the state transition strictly. This method has an issue that it is difficult to apply for large scale circuits, and solving simultaneous equations is one of bottleneck processes. In this paper, we propose acceleration methods by dividing simultaneous equations into small problems and removing unnecessary unknowns.
Keyword (in Japanese) (See Japanese page) 
(in English) soft error / sequential circuit / finite state machine / absorption probability / / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 462, VLD2009-126, pp. 163-168, March 2010.
Paper # VLD2009-126 
Date of Issue 2010-03-03 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2009-126

Conference Information
Committee VLD  
Conference Date 2010-03-10 - 2010-03-12 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for System-on-Silicon 
Paper Information
Registration To VLD 
Conference Code 2010-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An Acceleration of Soft Error Torelance Estimation Method for Sequential Circuits by Reducing the Number of States 
Sub Title (in English)  
Keyword(1) soft error  
Keyword(2) sequential circuit  
Keyword(3) finite state machine  
Keyword(4) absorption probability  
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1st Author's Name Yusuke Akamine  
1st Author's Affiliation Kyushu University (Kyushu Univ.)
2nd Author's Name Masayoshi Yoshimura  
2nd Author's Affiliation Kyushu University (Kyushu Univ.)
3rd Author's Name Yusuke Matsunaga  
3rd Author's Affiliation Kyushu University (Kyushu Univ.)
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Speaker Author-1 
Date Time 2010-03-12 13:55:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2009-126 
Volume (vol) vol.109 
Number (no) no.462 
Page pp.163-168 
#Pages 6 
Date of Issue 2010-03-03 (VLD) 

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