Paper Abstract and Keywords |
Presentation |
2010-03-12 13:30
Circuit conversion for reducing false negatives on formal verification of sequential circuit Norihiro Ono, Kazuhiro Nakamura, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.) VLD2009-125 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper proposes a reducing method of false negatives by the circuit conversion. We focus that the false negatives occur on unreachable states where the invariable conditions are false. The formal verification of sequential circuit will be able to speed up by reducing false negatives. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
false negative / formal verification / circuit conversion / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 109, no. 462, VLD2009-125, pp. 157-162, March 2010. |
Paper # |
VLD2009-125 |
Date of Issue |
2010-03-03 (VLD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2009-125 |
Conference Information |
Committee |
VLD |
Conference Date |
2010-03-10 - 2010-03-12 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
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Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Technology for System-on-Silicon |
Paper Information |
Registration To |
VLD |
Conference Code |
2010-03-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Circuit conversion for reducing false negatives on formal verification of sequential circuit |
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false negative |
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formal verification |
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circuit conversion |
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1st Author's Name |
Norihiro Ono |
1st Author's Affiliation |
Nagoya University (Nagoya Univ.) |
2nd Author's Name |
Kazuhiro Nakamura |
2nd Author's Affiliation |
Nagoya University (Nagoya Univ.) |
3rd Author's Name |
Kazuyoshi Takagi |
3rd Author's Affiliation |
Nagoya University (Nagoya Univ.) |
4th Author's Name |
Naofumi Takagi |
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Nagoya University (Nagoya Univ.) |
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Speaker |
Author-1 |
Date Time |
2010-03-12 13:30:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2009-125 |
Volume (vol) |
vol.109 |
Number (no) |
no.462 |
Page |
pp.157-162 |
#Pages |
6 |
Date of Issue |
2010-03-03 (VLD) |