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Paper Abstract and Keywords
Presentation 2010-03-27 16:00
A Topology Decision Approach of IP Cores for Throughput Improvement of Application Specific NoC System
Hiroshi Uchikoshi (TUT), Makoto Sugihara (TUT/JST) CPSY2009-88 DC2009-85
Abstract (in Japanese) (See Japanese page) 
(in English) The continuous effort in shrinking the size of a transistor causes a wire delay to increase relatively faster than a gate delay.
On-chip communication will be a major factor to determine the performance of a computer system.
Network-on-Chip is one of a communication architecture that interconnect with shortly link.
This paper proposes a design technique for embedded systems which uses a regular network topology as a communication topology and automatically maps IP cores onto the topology so that the high communication throughput is achieved.
Our design technique formulate communication throughput, then decide an IP core topology that maximize communication throughput.
We also experimintally confirmed that out design technique achieved high communication throughput.
Keyword (in Japanese) (See Japanese page) 
(in English) Network-on-Chip / Embedded system / throughput / IP core / topology / optimization / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 474, CPSY2009-88, pp. 321-326, March 2010.
Paper # CPSY2009-88 
Date of Issue 2010-03-19 (CPSY, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2009-88 DC2009-85

Conference Information
Committee CPSY DC IPSJ-SLDM IPSJ-EMB IPSJ-UBI IPSJ-MBL  
Conference Date 2010-03-26 - 2010-03-28 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To CPSY 
Conference Code 2010-03-CPSY-DC-SLDM-EMB-UBI-MBL 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Topology Decision Approach of IP Cores for Throughput Improvement of Application Specific NoC System 
Sub Title (in English)  
Keyword(1) Network-on-Chip  
Keyword(2) Embedded system  
Keyword(3) throughput  
Keyword(4) IP core  
Keyword(5) topology  
Keyword(6) optimization  
Keyword(7)  
Keyword(8)  
1st Author's Name Hiroshi Uchikoshi  
1st Author's Affiliation Toyohashi University of Technology (TUT)
2nd Author's Name Makoto Sugihara  
2nd Author's Affiliation Toyohashi University of Technology/JST (TUT/JST)
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Speaker Author-1 
Date Time 2010-03-27 16:00:00 
Presentation Time 20 minutes 
Registration for CPSY 
Paper # CPSY2009-88, DC2009-85 
Volume (vol) vol.109 
Number (no) no.474(CPSY), no.475(DC) 
Page pp.321-326 
#Pages 6 
Date of Issue 2010-03-19 (CPSY, DC) 

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