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Paper Abstract and Keywords
Presentation 2010-05-19 17:00
Error Propagation Probability-based Selective TMR for Reliable Coarse-Grained Reconfigurable Architecture
Hiroshi Yuasa, Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato (Kyoto Univ.) VLD2010-4
Abstract (in Japanese) (See Japanese page) 
(in English) Advancing CMOS process technology implies decreasing operating voltages, leaving LSI increasingly vulnerable to temporary faults, also known as soft faults.
Therefore, LSI systems which can mitigate soft-errors flexibly is desired to accommodate today's wide range of applications.
This paper proposes a selective TMR algorithm that is to achieve high dependability for coarse-grained reconfigurable architectures with low area-overheads. The proposed algorithm decides which circuits should be triplicated based on estimated reliability. Reliability can be estimated for general coarse-grained architectures using error propagation probability models between arithmetic operations in data flow graphs. As a result, the proposed selective TMR method can reduce error output cycle count by 74% from the existing method.
Keyword (in Japanese) (See Japanese page) 
(in English) Selective TMR / Error Propagation / Coarse-grained Reconfigurable Architecture / Soft-error / Dependability / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 36, VLD2010-4, pp. 37-42, May 2010.
Paper # VLD2010-4 
Date of Issue 2010-05-12 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2010-4

Conference Information
Committee VLD IPSJ-SLDM  
Conference Date 2010-05-19 - 2010-05-20 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu International Conference Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System Design, etc. 
Paper Information
Registration To VLD 
Conference Code 2010-05-VLD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Error Propagation Probability-based Selective TMR for Reliable Coarse-Grained Reconfigurable Architecture 
Sub Title (in English)  
Keyword(1) Selective TMR  
Keyword(2) Error Propagation  
Keyword(3) Coarse-grained Reconfigurable Architecture  
Keyword(4) Soft-error  
Keyword(5) Dependability  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Hiroshi Yuasa  
1st Author's Affiliation Kyoto University (Kyoto Univ.)
2nd Author's Name Takashi Imagawa  
2nd Author's Affiliation Kyoto University (Kyoto Univ.)
3rd Author's Name Masayuki Hiromoto  
3rd Author's Affiliation Kyoto University (Kyoto Univ.)
4th Author's Name Hiroyuki Ochi  
4th Author's Affiliation Kyoto University (Kyoto Univ.)
5th Author's Name Takashi Sato  
5th Author's Affiliation Kyoto University (Kyoto Univ.)
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Speaker Author-1 
Date Time 2010-05-19 17:00:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2010-4 
Volume (vol) vol.110 
Number (no) no.36 
Page pp.37-42 
#Pages 6 
Date of Issue 2010-05-12 (VLD) 

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