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Paper Abstract and Keywords
Presentation 2010-05-20 10:00
3D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link
Makoto Saen, Kenichi Osada, Yasuyuki Okuma (Hitachi), Yasuhisa Shimazaki (Keio Univ./Renesas Technology), Itaru Nonomura (Renesas Technology), Kiichi Niitsu, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Tadahiro Kuroda (Keio Univ.) VLD2010-5
Abstract (in Japanese) (See Japanese page) 
(in English) This paper describes a three-dimensional (3D) system integration of a fully functional processor chip and two memory chips by using inductive coupling. To attain a 3D communication link with a smaller area and lower power-consumption, shortening the link distance and preventing signal degradation due to unused inductors are important challenges. Therefore, we developed a new 3D-integrated wire-penetrated multi-layer structure for a shorter link distance and an open-skipped-inductor scheme for suppressing signal degradation. The power and area efficiency of the link are 1 pJ/b and 0.15 mm2/Gbps, respectively, which are the same as those of two-chip integration.
Keyword (in Japanese) (See Japanese page) 
(in English) 3D system integration / inductive coupling / processor / memory / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 36, VLD2010-5, pp. 43-47, May 2010.
Paper # VLD2010-5 
Date of Issue 2010-05-12 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee VLD IPSJ-SLDM  
Conference Date 2010-05-19 - 2010-05-20 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu International Conference Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System Design, etc. 
Paper Information
Registration To VLD 
Conference Code 2010-05-VLD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) 3D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link 
Sub Title (in English)  
Keyword(1) 3D system integration  
Keyword(2) inductive coupling  
Keyword(3) processor  
Keyword(4) memory  
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1st Author's Name Makoto Saen  
1st Author's Affiliation Hitachi Ltd. (Hitachi)
2nd Author's Name Kenichi Osada  
2nd Author's Affiliation Hitachi Ltd. (Hitachi)
3rd Author's Name Yasuyuki Okuma  
3rd Author's Affiliation Hitachi Ltd. (Hitachi)
4th Author's Name Yasuhisa Shimazaki  
4th Author's Affiliation Keio University/Renesas Technology (Keio Univ./Renesas Technology)
5th Author's Name Itaru Nonomura  
5th Author's Affiliation Renesas Technology Corp. (Renesas Technology)
6th Author's Name Kiichi Niitsu  
6th Author's Affiliation Keio University (Keio Univ.)
7th Author's Name Yasufumi Sugimori  
7th Author's Affiliation Keio University (Keio Univ.)
8th Author's Name Yoshinori Kohama  
8th Author's Affiliation Keio University (Keio Univ.)
9th Author's Name Kazutaka Kasuga  
9th Author's Affiliation Keio University (Keio Univ.)
10th Author's Name Tadahiro Kuroda  
10th Author's Affiliation Keio University (Keio Univ.)
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Speaker Author-1 
Date Time 2010-05-20 10:00:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2010-5 
Volume (vol) vol.110 
Number (no) no.36 
Page pp.43-47 
#Pages 5 
Date of Issue 2010-05-12 (VLD) 

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