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Paper Abstract and Keywords
Presentation 2010-06-11 10:40
Hardware Implementation of Real-time Deinterlacing based on Inpainting
Tatsuo Maeno (Osaka Univ.), Hiroshi Tsutsui (Kyoto Univ.), Takao Onoye (Osaka Univ.) SIS2010-16
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we propose a novel hardware architecture for inpainting-based deinterlacing method, which can convert 1080i60 video data to 1080p60 in real-time. Interlaced video sequences are widely used for digital terrestrial television and camcorders. However, they cannot be displayed directly on LCDs, which display video sequences by progressive scanning. Therefore, it is necessary to convert video sequences from interlaced format to progressive format. Recently proposed inpainting-based deinterlacing uses cost optimization to interpolate missing lines, which can be solved likely shortest path problem. Since this method does not require motion estimation, it is expected that implementations of this method require smaller amount of memory bits compared to methods based on motion compensation. In this paper, the number of processing elements in our architecture, which affects both converted video quality and hardware cost, is evaluated. When the number of processing elements which gives best video quality with reasonable hardware cost is used, the gate count of the proposed architecture is 942,998, and required memory size is 399 Kbit.
Keyword (in Japanese) (See Japanese page) 
(in English) Deinterlace / IP conversion / Real-time processing / Inpainting / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 74, SIS2010-16, pp. 87-92, June 2010.
Paper # SIS2010-16 
Date of Issue 2010-06-03 (SIS) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SIS2010-16

Conference Information
Committee SIS  
Conference Date 2010-06-10 - 2010-06-11 
Place (in Japanese) (See Japanese page) 
Place (in English) Abashiri Public Auditorium 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To SIS 
Conference Code 2010-06-SIS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Hardware Implementation of Real-time Deinterlacing based on Inpainting 
Sub Title (in English)  
Keyword(1) Deinterlace  
Keyword(2) IP conversion  
Keyword(3) Real-time processing  
Keyword(4) Inpainting  
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1st Author's Name Tatsuo Maeno  
1st Author's Affiliation Osaka University (Osaka Univ.)
2nd Author's Name Hiroshi Tsutsui  
2nd Author's Affiliation Kyoto University (Kyoto Univ.)
3rd Author's Name Takao Onoye  
3rd Author's Affiliation Osaka University (Osaka Univ.)
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Speaker Author-1 
Date Time 2010-06-11 10:40:00 
Presentation Time 25 minutes 
Registration for SIS 
Paper # SIS2010-16 
Volume (vol) vol.110 
Number (no) no.74 
Page pp.87-92 
#Pages 6 
Date of Issue 2010-06-03 (SIS) 

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