Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2010-07-23 09:40
OTA Design Using gm/ID Lookup Table Methodology -- Design optimization featuring settling time analysis --
Toru Kashimura, Takayuki Konishi, Shoichi Masui (Tohoku Univ.) ICD2010-31
Abstract (in Japanese) (See Japanese page) 
(in English) Settling time is a primary design parameter in operational transconductance amplifiers (OTAs) used for high-speed applications such as pipeline A/D converters. For scaled CMOS technologies, an OTA design methodology using gm/ID lookup tables has been proposed to minimize its power consumption. A major problem in the conventionally proposed method is that settling time was not included in a target specification, but was converted into crossover frequency fc with an empirical approach. In this paper, we introduce an iterative optimization sequence to design OTAs, which can achieve the target settling time with the minimum power consumptions.
Keyword (in Japanese) (See Japanese page) 
(in English) operational transconductance amplifier / design optimization / settling time optimization / low power design / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 140, ICD2010-31, pp. 61-66, July 2010.
Paper # ICD2010-31 
Date of Issue 2010-07-15 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2010-31

Conference Information
Committee ICD ITE-IST  
Conference Date 2010-07-22 - 2010-07-23 
Place (in Japanese) (See Japanese page) 
Place (in English) Josho Gakuen Osaka Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Analog, Mixed analog and digital, RF, and sensor interface circuitry 
Paper Information
Registration To ICD 
Conference Code 2010-07-ICD-IST 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) OTA Design Using gm/ID Lookup Table Methodology 
Sub Title (in English) Design optimization featuring settling time analysis 
Keyword(1) operational transconductance amplifier  
Keyword(2) design optimization  
Keyword(3) settling time optimization  
Keyword(4) low power design  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Toru Kashimura  
1st Author's Affiliation Tohoku Univercity (Tohoku Univ.)
2nd Author's Name Takayuki Konishi  
2nd Author's Affiliation Tohoku Univercity (Tohoku Univ.)
3rd Author's Name Shoichi Masui  
3rd Author's Affiliation Tohoku Univercity (Tohoku Univ.)
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2010-07-23 09:40:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # ICD2010-31 
Volume (vol) vol.110 
Number (no) no.140 
Page pp.61-66 
#Pages 6 
Date of Issue 2010-07-15 (ICD) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan