| Paper Abstract and Keywords |
| Presentation |
2010-08-27 09:00
Post-manufacturing, 17-times Acceptable Raw Bit Error Rate Enhancement, Dynamic Codeword Transition ECC Scheme for Highly Reliable Solid-State Drives, SSDs Shuhei Tanakamaru (Univ. of Tokyo), Atsushi Esumi, Mitsuyoshi Ito, Kai Li (SIGLEAD), Ken Takeuchi (Univ. of Tokyo) SDM2010-138 ICD2010-53 |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
A dynamic codeword transition ECC scheme is proposed for highly reliable solid-state drives, SSDs. By monitoring the error number or the write / erase cycles, the ECC codeword dynamically increases from 512Byte (+parity) to 1KByte, 2KByte, 4KByte…32KByte. The proposed ECC with a larger codeword decreases the failure rate after ECC. Because the parity rate per codeword is the same in each ECC codeword, no additional memory area is required so that the reliability of SSD is improved after the manufacturing without cost penalty. Compared with the conventional ECC with the fixed large 32KByte codeword, the proposed scheme achieves a lower power consumption by introducing the “best-effort” type operation. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
ECC / Error correcting code / SSD / NAND Flash memory / / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 110, no. 183, ICD2010-53, pp. 77-82, Aug. 2010. |
| Paper # |
ICD2010-53 |
| Date of Issue |
2010-08-19 (SDM, ICD) |
| ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
| Download PDF |
SDM2010-138 ICD2010-53 |
| Conference Information |
| Committee |
ICD SDM |
| Conference Date |
2010-08-26 - 2010-08-27 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
Sapporo Center for Gender Equality |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
Low voltage/low power techniques, novel devices, circuits, and applications |
| Paper Information |
| Registration To |
ICD |
| Conference Code |
2010-08-ICD-SDM |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
Post-manufacturing, 17-times Acceptable Raw Bit Error Rate Enhancement, Dynamic Codeword Transition ECC Scheme for Highly Reliable Solid-State Drives, SSDs |
| Sub Title (in English) |
|
| Keyword(1) |
ECC |
| Keyword(2) |
Error correcting code |
| Keyword(3) |
SSD |
| Keyword(4) |
NAND Flash memory |
| Keyword(5) |
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| 1st Author's Name |
Shuhei Tanakamaru |
| 1st Author's Affiliation |
University of Tokyo (Univ. of Tokyo) |
| 2nd Author's Name |
Atsushi Esumi |
| 2nd Author's Affiliation |
SIGLEAD (SIGLEAD) |
| 3rd Author's Name |
Mitsuyoshi Ito |
| 3rd Author's Affiliation |
SIGLEAD (SIGLEAD) |
| 4th Author's Name |
Kai Li |
| 4th Author's Affiliation |
SIGLEAD (SIGLEAD) |
| 5th Author's Name |
Ken Takeuchi |
| 5th Author's Affiliation |
University of Tokyo (Univ. of Tokyo) |
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| Speaker |
Author-1 |
| Date Time |
2010-08-27 09:00:00 |
| Presentation Time |
25 minutes |
| Registration for |
ICD |
| Paper # |
SDM2010-138, ICD2010-53 |
| Volume (vol) |
vol.110 |
| Number (no) |
no.182(SDM), no.183(ICD) |
| Page |
pp.77-82 |
| #Pages |
6 |
| Date of Issue |
2010-08-19 (SDM, ICD) |