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| Presentation | 2010-08-27 15:35 Pattern Layout Methods of System LSI with SGT Takahiro Kodama, Shigeyoshi Watanabe (Shonan Inst. of Tech.)  SDM2010-149 ICD2010-64 Link to ES Tech. Rep. Archives: SDM2010-149 ICD2010-64 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | The pattern area reduction of inverter, NAND, and full adder with SGT and stacked SGT has been ‘newly’ estimated. Wring SGT and stacked SGT the pattern area can be drastically reduced compared with that of conventional planar transistor, SGT and stacked SGT are promising candidate for reeling high density system LSI. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | SGT / stacked SGT / system LSI / design rule / pattern area / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 110, no. 182, SDM2010-149, pp. 137-142, Aug. 2010. | |
| Paper # | SDM2010-149 | |
| Date of Issue | 2010-08-19 (SDM, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | SDM2010-149 ICD2010-64 Link to ES Tech. Rep. Archives: SDM2010-149 ICD2010-64 |
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| Conference Information | |
| Committee | ICD SDM |
| Conference Date | 2010-08-26 - 2010-08-27 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Sapporo Center for Gender Equality |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Low voltage/low power techniques, novel devices, circuits, and applications |
| Paper Information | |
| Registration To | SDM |
| Conference Code | 2010-08-ICD-SDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Pattern Layout Methods of System LSI with SGT |
| Sub Title (in English) | |
| Keyword(1) | SGT |
| Keyword(2) | stacked SGT |
| Keyword(3) | system LSI |
| Keyword(4) | design rule |
| Keyword(5) | pattern area |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Takahiro Kodama |
| 1st Author's Affiliation | Shonan Institute of Technology (Shonan Inst. of Tech.) |
| 2nd Author's Name | Shigeyoshi Watanabe |
| 2nd Author's Affiliation | Shonan Institute of Technology (Shonan Inst. of Tech.) |
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| Speaker | Author-1 |
| Date Time | 2010-08-27 15:35:00 |
| Presentation Time | 25 minutes |
| Registration for | SDM |
| Paper # | SDM2010-149, ICD2010-64 |
| Volume (vol) | vol.110 |
| Number (no) | no.182(SDM), no.183(ICD) |
| Page | pp.137-142 |
| #Pages | 6 |
| Date of Issue | 2010-08-19 (SDM, ICD) |
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