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Paper Abstract and Keywords
Presentation 2010-09-16 11:00
Development of an On-chip Pattern Recognition System using Dynamic and Partial Reconfiguration
Hiroyuki Kawai, Moritoshi Yasunaga (Tsukuba Univ.) RECONF2010-18
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we develop an on-chip pattern recognition system.
The feature of this system is that two Microblaze cores are implemented on an FPGA and it can execute evolutionary algorithm faster than the past system. As an experiment, sonar spectrum pattern recognition which is a real-world problem is adopted and our developed system is evaluated with the problem. We show that our system can execute evolutionary computing approximately 2 times faster than the past system and deal with a real-world application.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / Dynamic and Partial Reconfiguration / On-chip system / Multi-core CPU / Evolvable Hardware / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 204, RECONF2010-18, pp. 1-6, Sept. 2010.
Paper # RECONF2010-18 
Date of Issue 2010-09-09 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2010-18

Conference Information
Committee RECONF  
Conference Date 2010-09-16 - 2010-09-17 
Place (in Japanese) (See Japanese page) 
Place (in English) Shizuoka University (Faculty of Eng., Hall 2) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reconfigurable Systems, etc. 
Paper Information
Registration To RECONF 
Conference Code 2010-09-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Development of an On-chip Pattern Recognition System using Dynamic and Partial Reconfiguration 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) Dynamic and Partial Reconfiguration  
Keyword(3) On-chip system  
Keyword(4) Multi-core CPU  
Keyword(5) Evolvable Hardware  
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Keyword(8)  
1st Author's Name Hiroyuki Kawai  
1st Author's Affiliation Tsukuba University (Tsukuba Univ.)
2nd Author's Name Moritoshi Yasunaga  
2nd Author's Affiliation Tsukuba University (Tsukuba Univ.)
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Speaker Author-1 
Date Time 2010-09-16 11:00:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2010-18 
Volume (vol) vol.110 
Number (no) no.204 
Page pp.1-6 
#Pages 6 
Date of Issue 2010-09-09 (RECONF) 

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