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Paper Abstract and Keywords
Presentation 2010-11-30 13:15
Circuit Generation using High-Level Synthesis Tool in Reconfigurable HPC System Based on FPGA Arrays
Kenichi Takahashi, Jiang Li, Hiroki Isogai, Hiroki Banba, Hakaru Tamukoh, Masatoshi Sekine (TUAT) RECONF2010-39
Abstract (in Japanese) (See Japanese page) 
(in English) In recent years, HPC system architectures comprised of GPUs or FPGAs are becoming common. We propose a Reconfigurable HPC system based on a hardware/software complex system model including FPGAs, and compare its performance with CPU Clusters and CUDA based GPGPU implementations. In addition, we discuss the merits of using a hw/sw complex system which include integral components generated by high-level programming languages.
Keyword (in Japanese) (See Japanese page) 
(in English) hw/sw complex system / FPGA / Reconfigurable HPC / GPGPU / High-Level Synthesis Tool / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 319, RECONF2010-39, pp. 1-6, Nov. 2010.
Paper # RECONF2010-39 
Date of Issue 2010-11-23 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2010-39

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2010-11-29 - 2010-12-01 
Place (in Japanese) (See Japanese page) 
Place (in English) Kyushu University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2010 ―New Field of VLSI Design― 
Paper Information
Registration To RECONF 
Conference Code 2010-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Circuit Generation using High-Level Synthesis Tool in Reconfigurable HPC System Based on FPGA Arrays 
Sub Title (in English)  
Keyword(1) hw/sw complex system  
Keyword(2) FPGA  
Keyword(3) Reconfigurable HPC  
Keyword(4) GPGPU  
Keyword(5) High-Level Synthesis Tool  
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Keyword(7)  
Keyword(8)  
1st Author's Name Kenichi Takahashi  
1st Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
2nd Author's Name Jiang Li  
2nd Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
3rd Author's Name Hiroki Isogai  
3rd Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
4th Author's Name Hiroki Banba  
4th Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
5th Author's Name Hakaru Tamukoh  
5th Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
6th Author's Name Masatoshi Sekine  
6th Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
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Speaker Author-1 
Date Time 2010-11-30 13:15:00 
Presentation Time 20 minutes 
Registration for RECONF 
Paper # RECONF2010-39 
Volume (vol) vol.110 
Number (no) no.319 
Page pp.1-6 
#Pages
Date of Issue 2010-11-23 (RECONF) 


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