Paper Abstract and Keywords |
Presentation |
2010-11-30 10:10
A study of high-performance asynchronous network-on-chip focused on bias of packets transfer routes Satoshi Takeyasu, Masashi Imai, Hiroshi Nakamura (Tokyo Univ.) VLD2010-66 DC2010-33 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
GALS-NoC is recently paid attention. Beside, NoC have commonly bias of packets transfer routes by regularity of network topology and routing algorithm. By focusing on the bias, we propose high performance and area efficient asynchronous NoC. the NoC(2D-mesh, xy-routing) is designed with a 65nm CMOS process and evaluated in terms of the area and peak-throughput. the proposed method can increase the peak- throughput by 2.8% and the area by 6.7%. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
asynchronous / GALS / NoC / bias / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 110, no. 316, VLD2010-66, pp. 67-72, Nov. 2010. |
Paper # |
VLD2010-66 |
Date of Issue |
2010-11-22 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2010-66 DC2010-33 |
Conference Information |
Committee |
VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
Conference Date |
2010-11-29 - 2010-12-01 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kyushu University |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2010 ―New Field of VLSI Design― |
Paper Information |
Registration To |
VLD |
Conference Code |
2010-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A study of high-performance asynchronous network-on-chip focused on bias of packets transfer routes |
Sub Title (in English) |
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asynchronous |
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GALS |
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NoC |
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bias |
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1st Author's Name |
Satoshi Takeyasu |
1st Author's Affiliation |
Tokyo University (Tokyo Univ.) |
2nd Author's Name |
Masashi Imai |
2nd Author's Affiliation |
Tokyo University (Tokyo Univ.) |
3rd Author's Name |
Hiroshi Nakamura |
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Tokyo University (Tokyo Univ.) |
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Speaker |
Author-1 |
Date Time |
2010-11-30 10:10:00 |
Presentation Time |
20 minutes |
Registration for |
VLD |
Paper # |
VLD2010-66, DC2010-33 |
Volume (vol) |
vol.110 |
Number (no) |
no.316(VLD), no.317(DC) |
Page |
pp.67-72 |
#Pages |
6 |
Date of Issue |
2010-11-22 (VLD, DC) |
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