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Paper Abstract and Keywords
Presentation 2010-12-01 14:15
Develop A Clock Tree Generator into Open-source CAD System.
Takuya Higuchi, Jun'ichiro Ogane, Naohiko Shimizu (Tokai Univ.) VLD2010-80 DC2010-47
Abstract (in Japanese) (See Japanese page) 
(in English) We developed the LSI design methodology with using NSL
which is a high-level hardware description language, and Alliance
CAD System which is EDA tools with scalable cell library.
We made ``on semi1.2$\mu$m'' process and
Rohm 0.35$\mu$m, which are sub micron and deep-sub micron process.
However, because of simply routing clock signals without consideration of digital system performance,
there is the problem clock skew caused by RC delay on deep-sub micron process.
In order to solve this problem,
the authors implement the function clock tree synthesis as part of toolchain into Alliance.
Keyword (in Japanese) (See Japanese page) 
(in English) SoC / EDA / OSS / / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 316, VLD2010-80, pp. 167-172, Nov. 2010.
Paper # VLD2010-80 
Date of Issue 2010-11-22 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2010-80 DC2010-47

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2010-11-29 - 2010-12-01 
Place (in Japanese) (See Japanese page) 
Place (in English) Kyushu University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2010 ―New Field of VLSI Design― 
Paper Information
Registration To VLD 
Conference Code 2010-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Develop A Clock Tree Generator into Open-source CAD System. 
Sub Title (in English)  
Keyword(1) SoC  
Keyword(2) EDA  
Keyword(3) OSS  
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1st Author's Name Takuya Higuchi  
1st Author's Affiliation Tokai University (Tokai Univ.)
2nd Author's Name Jun'ichiro Ogane  
2nd Author's Affiliation Tokai University (Tokai Univ.)
3rd Author's Name Naohiko Shimizu  
3rd Author's Affiliation Tokai University (Tokai Univ.)
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Speaker Author-1 
Date Time 2010-12-01 14:15:00 
Presentation Time 20 minutes 
Registration for VLD 
Paper # VLD2010-80, DC2010-47 
Volume (vol) vol.110 
Number (no) no.316(VLD), no.317(DC) 
Page pp.167-172 
#Pages 6 
Date of Issue 2010-11-22 (VLD, DC) 

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