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| Presentation | 2010-12-16 15:10 [Poster Presentation] Design of Memory Access Controller for FU Array Accelerator Shunsuke Shitaoka, Takuya Iwakami, Kazuhiro Yoshimura, Takashi Nakada, Yasuhiko Nakashima (NAIST)  ICD2010-114 Link to ES Tech. Rep. Archives: ICD2010-114 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Our previously proposed FU (functional unit) array accelerator can achieve both high energy-efficiency and binary-compatibility by exploiting maximum parallelism, using minimum necessary units to effectively map conventional codes, and gating unmapped units. This poster specifies the design of its memory access controller. Under the preparation mode, the controller prefetches data from external memory to L1 cache. In the acceleration mode, it provides data from L1 cache to local cache, enabling a zero cache miss array execution. The result shows that the memory access controller takes 17% of the total area. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Functional unit (FU) array / Memory access controller / Local cache / Reconfigurable architecture / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 110, no. 344, ICD2010-114, pp. 95-96, Dec. 2010. | |
| Paper # | ICD2010-114 | |
| Date of Issue | 2010-12-09 (ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | ICD2010-114 Link to ES Tech. Rep. Archives: ICD2010-114 |
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| Conference Information | |
| Committee | ICD |
| Conference Date | 2010-12-16 - 2010-12-17 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | RCAST, Univ. of Tokyo |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Workshop for Graduate Student and Young Researchers |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2010-12-ICD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of Memory Access Controller for FU Array Accelerator |
| Sub Title (in English) | |
| Keyword(1) | Functional unit (FU) array |
| Keyword(2) | Memory access controller |
| Keyword(3) | Local cache |
| Keyword(4) | Reconfigurable architecture |
| Keyword(5) | |
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| 1st Author's Name | Shunsuke Shitaoka |
| 1st Author's Affiliation | Nara Institute of Science and Technology (NAIST) |
| 2nd Author's Name | Takuya Iwakami |
| 2nd Author's Affiliation | Nara Institute of Science and Technology (NAIST) |
| 3rd Author's Name | Kazuhiro Yoshimura |
| 3rd Author's Affiliation | Nara Institute of Science and Technology (NAIST) |
| 4th Author's Name | Takashi Nakada |
| 4th Author's Affiliation | Nara Institute of Science and Technology (NAIST) |
| 5th Author's Name | Yasuhiko Nakashima |
| 5th Author's Affiliation | Nara Institute of Science and Technology (NAIST) |
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| Speaker | Author-1 |
| Date Time | 2010-12-16 15:10:00 |
| Presentation Time | 120 minutes |
| Registration for | ICD |
| Paper # | ICD2010-114 |
| Volume (vol) | vol.110 |
| Number (no) | no.344 |
| Page | pp.95-96 |
| #Pages | 2 |
| Date of Issue | 2010-12-09 (ICD) |
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