Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2010-12-17 15:40
Design of a Low Error LUT-based Truncated Multiplier
Van-Phuc Hoang, Cong-Kha Pham (Univ. of Electro-comm.) ICD2010-126
Abstract (in Japanese) (See Japanese page) 
(in English) Truncated multiplication is an efficient method to reduce area and power consumption of multipliers in signal processing systems. In this paper, we present a low area and low error 8×8 fixed width multiplier using LUT-based truncated method. The simulation and implementation results in FPGA hardware and Synopsys Design Compiler tool show that the proposed architecture outperforms the array and traditional truncated multipliers in both area efficiency and average error.
Keyword (in Japanese) (See Japanese page) 
(in English) LUT-based computation / truncated multiplier / low area digital hardware / FPGA / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 344, ICD2010-126, pp. 159-162, Dec. 2010.
Paper # ICD2010-126 
Date of Issue 2010-12-09 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2010-126

Conference Information
Committee ICD  
Conference Date 2010-12-16 - 2010-12-17 
Place (in Japanese) (See Japanese page) 
Place (in English) RCAST, Univ. of Tokyo 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Workshop for Graduate Student and Young Researchers 
Paper Information
Registration To ICD 
Conference Code 2010-12-ICD 
Language English (Japanese title is available) 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design of a Low Error LUT-based Truncated Multiplier 
Sub Title (in English)  
Keyword(1) LUT-based computation  
Keyword(2) truncated multiplier  
Keyword(3) low area digital hardware  
Keyword(4) FPGA  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Van-Phuc Hoang  
1st Author's Affiliation University of Electro-communications, Tokyo (Univ. of Electro-comm.)
2nd Author's Name Cong-Kha Pham  
2nd Author's Affiliation University of Electro-communications, Tokyo (Univ. of Electro-comm.)
3rd Author's Name  
3rd Author's Affiliation ()
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2010-12-17 15:40:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # ICD2010-126 
Volume (vol) vol.110 
Number (no) no.344 
Page pp.159-162 
#Pages 4 
Date of Issue 2010-12-09 (ICD) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan