講演抄録/キーワード |
講演名 |
2010-12-17 13:50
Misleading Energy and Performance Claims in Sub/Near Threshold Digital Systems ○Yu Pu・Xin Zhang・Jim Huang(Univ. of Tokyo)・Atsushi Muramatsu・Masahiro Nomura・Koji Hirairi・Hidehiro Takata・Taro Sakurabayashi・Shinji Miyano(STARC)・Makoto Takamiya・Takayasu Sakurai(Univ. of Tokyo) ICD2010-122 エレソ技報アーカイブへのリンク:ICD2010-122 |
抄録 |
(和) |
Many of us in the field of ultra-low-Vdd processors experience difficulty in assessing the sub/near threshold circuit techniques proposed by earlier papers. This paper investigates three major pitfalls which are often not appreciated by researchers when claiming that their circuits outperform others by working at a lower Vdd with a higher energy-efficiency. These pitfalls include: i) overlook the impacts of different technologies and different Vth definitions, ii) only emphasize energy reduction but ignore severe throughput degradation, or expect impractical pipelining depth and parallelism degree to compensate this throughput degradation, iii) unrealistically assume that memory's Vdd and energy could scale as well as standard cells. Therefore, the actual energy benefit from using a sub/near threshold Vdd can be greatly overestimated. This work provides some design guidelines and silicon evidence to ultra-low-Vdd systems. The outlined pitfalls also shed light on future directions in this field. |
(英) |
Many of us in the field of ultra-low-Vdd processors experience difficulty in assessing the sub/near threshold circuit techniques proposed by earlier papers. This paper investigates three major pitfalls which are often not appreciated by researchers when claiming that their circuits outperform others by working at a lower Vdd with a higher energy-efficiency. These pitfalls include: i) overlook the impacts of different technologies and different Vth definitions, ii) only emphasize energy reduction but ignore severe throughput degradation, or expect impractical pipelining depth and parallelism degree to compensate this throughput degradation, iii) unrealistically assume that memory's Vdd and energy could scale as well as standard cells. Therefore, the actual energy benefit from using a sub/near threshold Vdd can be greatly overestimated. This work provides some design guidelines and silicon evidence to ultra-low-Vdd systems. The outlined pitfalls also shed light on future directions in this field. |
キーワード |
(和) |
low energy / sub-threshold / near-threshold / digital circuits / / / / |
(英) |
low energy / sub-threshold / near-threshold / digital circuits / / / / |
文献情報 |
信学技報, vol. 110, no. 344, ICD2010-122, pp. 135-140, 2010年12月. |
資料番号 |
ICD2010-122 |
発行日 |
2010-12-09 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
著作権に ついて |
技術研究報告に掲載された論文の著作権は電子情報通信学会に帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
PDFダウンロード |
ICD2010-122 エレソ技報アーカイブへのリンク:ICD2010-122 |