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Paper Abstract and Keywords
Presentation 2011-01-18 10:20
Evaluation of switchable AES S-box circuit using dynamic and partial reconfiguration
Naoko Yamada (Keio Univ.), Keisuke Iwai, Takakazu Kurokawa (NDA), Hideharu Amano (Keio Univ.) VLD2010-102 CPSY2010-57 RECONF2010-71
Abstract (in Japanese) (See Japanese page) 
(in English) Recently, the threat of side channel attack to the hardware encryption circuits is increasing. In order
to cope with it, various counter-side channel attack methods have been invented of AES (Advanced Encryption
Standard) Standard, and all of them are implemented in the S-box module. Since they have different benefits, the
strength can be improved by using them in order. However, providing various s-Box modules consumes a large
hardware resource. Here, a cost efficient implementation method for multiple S-box modules is proposed. By using
dynamic partial reconfiguration a various S-box modules can be replaced without stopping the encryption. For
continuous operation, Key Expansion circuits are separated and used as a reconfiguration target. Evaluation results
on a Virtex-5 FPGA show that multiple S-box modules can be implemented only with 11.154% overhead.
Keyword (in Japanese) (See Japanese page) 
(in English) Dynamic and Partial Reconfiguration / AES / S-box / / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 362, RECONF2010-71, pp. 127-132, Jan. 2011.
Paper # RECONF2010-71 
Date of Issue 2011-01-10 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2010-102 CPSY2010-57 RECONF2010-71

Conference Information
Committee RECONF VLD CPSY IPSJ-SLDM  
Conference Date 2011-01-17 - 2011-01-18 
Place (in Japanese) (See Japanese page) 
Place (in English) Keio Univ (Hiyoshi Campus) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To RECONF 
Conference Code 2011-01-RECONF-VLD-CPSY-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Evaluation of switchable AES S-box circuit using dynamic and partial reconfiguration 
Sub Title (in English)  
Keyword(1) Dynamic and Partial Reconfiguration  
Keyword(2) AES  
Keyword(3) S-box  
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1st Author's Name Naoko Yamada  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Keisuke Iwai  
2nd Author's Affiliation National Defense Academy (NDA)
3rd Author's Name Takakazu Kurokawa  
3rd Author's Affiliation National Defense Academy (NDA)
4th Author's Name Hideharu Amano  
4th Author's Affiliation Keio University (Keio Univ.)
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Speaker Author-1 
Date Time 2011-01-18 10:20:00 
Presentation Time 20 minutes 
Registration for RECONF 
Paper # VLD2010-102, CPSY2010-57, RECONF2010-71 
Volume (vol) vol.110 
Number (no) no.360(VLD), no.361(CPSY), no.362(RECONF) 
Page pp.127-132 
#Pages 6 
Date of Issue 2011-01-10 (VLD, CPSY, RECONF) 

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