Paper Abstract and Keywords |
Presentation |
2011-02-14 13:45
Test Pattern Generation for Highly Accurate Delay Testing Keigo Hori (NAIST), Tomokazu Yoneda, Michiko Inoue, Hideo Fujiwara (NAIST/JST) DC2010-64 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
We propose a new faster-than-at-speed test method to detect small delay defects. As semiconductor technology is scaling down, transistor aging such as NBTI and TDDB becomes major concern on field reliability. Since these aging mechanisms manifest as gradual delay increase, it is possible to predict system failure by detecting small delay increase. In this paper, we consider two criterions on capability of small delay defect detection, and propose two test pattern generation method for both criterions, respectively. Experimental results demonstrate the effectiveness of the proposed method. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Delay Test / Test Response Masking / Small Delay Defect / Aging / Field test / / / |
Reference Info. |
IEICE Tech. Rep., vol. 110, no. 413, DC2010-64, pp. 33-38, Feb. 2011. |
Paper # |
DC2010-64 |
Date of Issue |
2011-02-07 (DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
DC2010-64 |
|