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Paper Abstract and Keywords
Presentation 2011-03-19 15:10
An Architecture for Low-Latency Anonymizing Mechanism
Junichi Sawada, Koichi Inoue, Hiroaki Nishi (Keio Univ.) CPSY2010-81 DC2010-80
Abstract (in Japanese) (See Japanese page) 
(in English) In experiencing the growth of quantity and value of data, data holders realize the importance to utilize information that is abandoned or concealed currently. In this situation, they face the difficulty of releasing data without revealing privacy information. One of the methods to protect privacy information in publishing data is known as a privacy preserving method based on a constraint termed k-anonymity and l-diversity. It enables users of the data to utilize published data as they like. However, it requires a large running time. This research proposes TCAM-based hardware architecture for accelerating k-anonymity and l-diversity algorithm and improves its performance. The evaluation on FPGA device proves that the proposed architecture achieves approximately 10-50 times faster throughput than a RAM-based architecture.
Keyword (in Japanese) (See Japanese page) 
(in English) Hardware / Data Privacy / Privacy-Preserving Data Publishing / k-anonymity / l-diversity / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 473, CPSY2010-81, pp. 309-314, March 2011.
Paper # CPSY2010-81 
Date of Issue 2011-03-11 (CPSY, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2010-81 DC2010-80

Conference Information
Committee CPSY DC IPSJ-SLDM IPSJ-EMB  
Conference Date 2011-03-18 - 2011-03-19 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To CPSY 
Conference Code 2011-03-CPSY-DC-SLDM-EMB 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An Architecture for Low-Latency Anonymizing Mechanism 
Sub Title (in English)  
Keyword(1) Hardware  
Keyword(2) Data Privacy  
Keyword(3) Privacy-Preserving Data Publishing  
Keyword(4) k-anonymity  
Keyword(5) l-diversity  
Keyword(6)  
Keyword(7)  
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1st Author's Name Junichi Sawada  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Koichi Inoue  
2nd Author's Affiliation Keio University (Keio Univ.)
3rd Author's Name Hiroaki Nishi  
3rd Author's Affiliation Keio University (Keio Univ.)
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Speaker Author-1 
Date Time 2011-03-19 15:10:00 
Presentation Time 25 minutes 
Registration for CPSY 
Paper # CPSY2010-81, DC2010-80 
Volume (vol) vol.110 
Number (no) no.473(CPSY), no.474(DC) 
Page pp.309-314 
#Pages 6 
Date of Issue 2011-03-11 (CPSY, DC) 

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