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Paper Abstract and Keywords
Presentation 2011-04-19 09:30
0.45-V Operating Vt-Variation Tolerant 9T/18T Dual-Port SRAM
Koji Yanagida, Hiroki Noguchi, Shunsuke Okumura, Tomoya Takagi, Koji Kugata (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST), Hiroshi Kawaguchi (Kobe Univ.) ICD2011-8
Abstract (in Japanese) (See Japanese page) 
(in English) We proposes a dependable dual-port SRAM with 9T/18T bitcell structure. The proposed SRAM has two operating modes: a 9T normal mode and an 18T dependable mode. The 9T bitcell has an outside single-ended bitline as a dedicated read port along with a pair of conventional differential inside bitlines. Therefore, the 18T bitcell has two differential pairs of the outside bitlines and inside bitlines. The 9T/18T dual-port SRAM can scale its speed, operating voltage, and power dynamically by combining two bitcells for one-bit information.We designed and fabricated the proposed SRAM using a 65-nm process. The measurement results show that the dependable read mode using the pair of the single-ended bitlines can reduce the operation voltage to 0.45 V at a frequency of 1 MHz although the dependable read mode using the inside bitlines needs 0.54 V at the same frequency.
Keyword (in Japanese) (See Japanese page) 
(in English) SRAM / dependability / quality of a bit / / / / /  
Reference Info. IEICE Tech. Rep., vol. 111, no. 6, ICD2011-8, pp. 43-48, April 2011.
Paper # ICD2011-8 
Date of Issue 2011-04-11 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2011-8

Conference Information
Committee ICD  
Conference Date 2011-04-18 - 2011-04-19 
Place (in Japanese) (See Japanese page) 
Place (in English) Kobe University Takigawa Memorial Hall 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Memory Device Technologies 
Paper Information
Registration To ICD 
Conference Code 2011-04-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) 0.45-V Operating Vt-Variation Tolerant 9T/18T Dual-Port SRAM 
Sub Title (in English)  
Keyword(1) SRAM  
Keyword(2) dependability  
Keyword(3) quality of a bit  
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1st Author's Name Koji Yanagida  
1st Author's Affiliation Kobe University (Kobe Univ.)
2nd Author's Name Hiroki Noguchi  
2nd Author's Affiliation Kobe University (Kobe Univ.)
3rd Author's Name Shunsuke Okumura  
3rd Author's Affiliation Kobe University (Kobe Univ.)
4th Author's Name Tomoya Takagi  
4th Author's Affiliation Kobe University (Kobe Univ.)
5th Author's Name Koji Kugata  
5th Author's Affiliation Kobe University (Kobe Univ.)
6th Author's Name Masahiko Yoshimoto  
6th Author's Affiliation Kobe University/JST CREST (Kobe Univ./JST)
7th Author's Name Hiroshi Kawaguchi  
7th Author's Affiliation Kobe University (Kobe Univ.)
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Speaker Author-1 
Date Time 2011-04-19 09:30:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # ICD2011-8 
Volume (vol) vol.111 
Number (no) no.6 
Page pp.43-48 
#Pages 6 
Date of Issue 2011-04-11 (ICD) 

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