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Paper Abstract and Keywords
Presentation 2011-09-08 15:00
A Study of Scale Reduction of Analog Circuits for an Adaptive Array with a Single Receiver Using Time-Division Multiplexing
Ken-ichi Koga (Tokai Rika/Nagoya Inst. of Tech.), Nobuyoshi Kikuma, Hiroshi Hirayama, Kunio Sakakibara (Nagoya Inst. of Tech.), Tatsuya Koike, Hiroaki Iwashita, Yoshiyuki Mizuno (Tokai Rika) AP2011-65
Abstract (in Japanese) (See Japanese page) 
(in English) We propose the scale reduction method of analog circuits for an adaptive array antenna. A conventional adaptive array antenna needs the analog circuits, such as the filter, amplifier, down converter and AD converter, for each antenna. Accordingly, it is a problem that the scale of the analog circuits for the conventional adaptive array antenna system is larger than the one for the single antenna system. In the past study, the method of scale reduction of the analog circuits, which are time-division multiplexed and share the parts except the amplifier and the filter, is proposed. However, this method requires the high performance amplifier because of the power loss due to switching. Therefore, in this paper, we propose the compressing method of switching power loss for the scale reduction of analog circuits by sharing the single amplifier. Via computer simulation, it is confirmed by the comparison with the conventional adaptive array antenna that our proposed method is effective.
Keyword (in Japanese) (See Japanese page) 
(in English) time-division multiplexing / adaptive array / single receiver / scale reduction of analog circuits / / / /  
Reference Info. IEICE Tech. Rep., vol. 111, no. 200, AP2011-65, pp. 7-12, Sept. 2011.
Paper # AP2011-65 
Date of Issue 2011-09-01 (AP) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee MW AP  
Conference Date 2011-09-08 - 2011-09-09 
Place (in Japanese) (See Japanese page) 
Place (in English) Osaka Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To AP 
Conference Code 2011-09-MW-AP 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Study of Scale Reduction of Analog Circuits for an Adaptive Array with a Single Receiver Using Time-Division Multiplexing 
Sub Title (in English)  
Keyword(1) time-division multiplexing  
Keyword(2) adaptive array  
Keyword(3) single receiver  
Keyword(4) scale reduction of analog circuits  
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1st Author's Name Ken-ichi Koga  
1st Author's Affiliation Tokai Rika Co.,Ltd./Nagoya Institute of Technology (Tokai Rika/Nagoya Inst. of Tech.)
2nd Author's Name Nobuyoshi Kikuma  
2nd Author's Affiliation Nagoya Institute of Technology (Nagoya Inst. of Tech.)
3rd Author's Name Hiroshi Hirayama  
3rd Author's Affiliation Nagoya Institute of Technology (Nagoya Inst. of Tech.)
4th Author's Name Kunio Sakakibara  
4th Author's Affiliation Nagoya Institute of Technology (Nagoya Inst. of Tech.)
5th Author's Name Tatsuya Koike  
5th Author's Affiliation Tokai Rika Co.,Ltd. (Tokai Rika)
6th Author's Name Hiroaki Iwashita  
6th Author's Affiliation Tokai Rika Co.,Ltd. (Tokai Rika)
7th Author's Name Yoshiyuki Mizuno  
7th Author's Affiliation Tokai Rika Co.,Ltd. (Tokai Rika)
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Speaker Author-1 
Date Time 2011-09-08 15:00:00 
Presentation Time 25 minutes 
Registration for AP 
Paper # AP2011-65 
Volume (vol) vol.111 
Number (no) no.200 
Page pp.7-12 
#Pages 6 
Date of Issue 2011-09-01 (AP) 

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