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| Presentation | 2011-09-26 13:55 FPGA placement based on Self-Organized Map Yasuaki Tomonari, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)  RECONF2011-26 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Cell placement is an important phase of current FPGA(Field Programmable Gate Array) circuit design.However, this placement problem is NP-hard.Although nondeterministic algorithms such as Simulated Annealing(SA) are successful in slolving this problem, they are known to be slow. In this paper, we introduce a new neural network approach to placement problem of FPGA. The used network is a Kohonen self-organising map. A connection relation ship of cluster-level netlists is converted to a a set of appropriate input vectors. These vectors which have higher dimensionality are fed to the self-organizing map at random to map themselves onto a 2-dimensional plane of the regular chip. The key feature is that som algorithm perform the cell placement to minimize total connection length in the circuit. In this paper, we evaluate our placement tool using some benchmark circuits. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | FPGA placement / Self-Organizing Maps / SOM / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 111, no. 218, RECONF2011-26, pp. 25-30, Sept. 2011. | |
| Paper # | RECONF2011-26 | |
| Date of Issue | 2011-09-19 (RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | RECONF2011-26 |
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| Conference Information | |
| Committee | RECONF |
| Conference Date | 2011-09-26 - 2011-09-27 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Nagoya Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Reconfigurable Systems, etc. |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2011-09-RECONF |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | FPGA placement based on Self-Organized Map |
| Sub Title (in English) | |
| Keyword(1) | FPGA placement |
| Keyword(2) | Self-Organizing Maps |
| Keyword(3) | SOM |
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| 1st Author's Name | Yasuaki Tomonari |
| 1st Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 2nd Author's Name | Motoki Amagasaki |
| 2nd Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 3rd Author's Name | Masahiro Iida |
| 3rd Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 4th Author's Name | Morihiro Kuga |
| 4th Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 5th Author's Name | Toshinori Sueyoshi |
| 5th Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
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| Speaker | Author-1 |
| Date Time | 2011-09-26 13:55:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | RECONF2011-26 |
| Volume (vol) | vol.111 |
| Number (no) | no.218 |
| Page | pp.25-30 |
| #Pages | 6 |
| Date of Issue | 2011-09-19 (RECONF) |
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