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Paper Abstract and Keywords
Presentation 2011-09-27 14:10
Variable and Clause Elimination in SAT problems using an FPGA
Masayuki Suzuki, Tsutomu Maruyama (Univ. of Tsukuba) RECONF2011-40
Abstract (in Japanese) (See Japanese page) 
(in English) The satisfiability (SAT) problem is to find an assignment of binary values to the variables which satisfy a given clausal normal form (CNF). Many practical application problems can be transformed to SAT problems, and many SAT solvers have been developed. SAT problem is, however, NP-complete and its computational cost is very high. In order to reduce the computational cost, preprocessors are widely used by SAT solvers. In this paper, we describe an approach for implementing a preprocessor (SatELite) on FPGA. In SatELite, the variables and clauses whose values can be uniquely determined from other variables and clauses are eliminated to reduce the search space of the given SAT problem. The algorithms used in SatELite have inherent parallelism, but the data size of the SAT problems is very large, and the performance of the system is limited by the throughput of the o-chip DRAM banks. In our implementation, several clauses are held on the FPGA, and are compared in parallel with a sequence of new clauses. The sequence is cached on the FPGA, and reused in order to hide the access delay to the DRAM banks. The speedup by our system depends on the problem size, however it becomes higher for larger problems.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / SAT Problems / preprocessor / / / / /  
Reference Info. IEICE Tech. Rep., vol. 111, no. 218, RECONF2011-40, pp. 105-110, Sept. 2011.
Paper # RECONF2011-40 
Date of Issue 2011-09-19 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2011-40

Conference Information
Committee RECONF  
Conference Date 2011-09-26 - 2011-09-27 
Place (in Japanese) (See Japanese page) 
Place (in English) Nagoya Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reconfigurable Systems, etc. 
Paper Information
Registration To RECONF 
Conference Code 2011-09-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Variable and Clause Elimination in SAT problems using an FPGA 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) SAT Problems  
Keyword(3) preprocessor  
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1st Author's Name Masayuki Suzuki  
1st Author's Affiliation University of Tsukuba (Univ. of Tsukuba)
2nd Author's Name Tsutomu Maruyama  
2nd Author's Affiliation University of Tsukuba (Univ. of Tsukuba)
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Speaker Author-1 
Date Time 2011-09-27 14:10:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2011-40 
Volume (vol) vol.111 
Number (no) no.218 
Page pp.105-110 
#Pages 6 
Date of Issue 2011-09-19 (RECONF) 

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