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Paper Abstract and Keywords
Presentation 2011-09-27 09:25
A Design Framework for relieving a HW Bottleneck FPGAs Connected with a High-Speed Data Bus
Koichi Araki, Yukinori Sato, Yasushi Inoguchi (JAIST) RECONF2011-33
Abstract (in Japanese) (See Japanese page) 
(in English) As reconfigurable devices with a PCI-Express interface appear in the market, the data transfer speed between the reconfigurable devices and other units increases.
However, if the Hardware execution time is longer than the data transfer time, the data transfer is suspended to wait the hardware execution.
In this paper, we propose a novel framework for implementing hardware structure which can process a data parallel loop using an reconfigurable device without suspending the data transfer.
As a result of performance evaluation, we show that hardware generated by the our framework performs well in terms of the hi-speed data transfer and the the hardware execution on an FPGA.
Keyword (in Japanese) (See Japanese page) 
(in English) PCI-Express / Data Parallelism / Data Transfer / / / / /  
Reference Info. IEICE Tech. Rep., vol. 111, no. 218, RECONF2011-33, pp. 63-68, Sept. 2011.
Paper # RECONF2011-33 
Date of Issue 2011-09-19 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2011-33

Conference Information
Committee RECONF  
Conference Date 2011-09-26 - 2011-09-27 
Place (in Japanese) (See Japanese page) 
Place (in English) Nagoya Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reconfigurable Systems, etc. 
Paper Information
Registration To RECONF 
Conference Code 2011-09-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Design Framework for relieving a HW Bottleneck FPGAs Connected with a High-Speed Data Bus 
Sub Title (in English)  
Keyword(1) PCI-Express  
Keyword(2) Data Parallelism  
Keyword(3) Data Transfer  
1st Author's Name Koichi Araki  
1st Author's Affiliation Japan Advanced Institute of Science and Technology (JAIST)
2nd Author's Name Yukinori Sato  
2nd Author's Affiliation Japan Advanced Institute of Science and Technology (JAIST)
3rd Author's Name Yasushi Inoguchi  
3rd Author's Affiliation Japan Advanced Institute of Science and Technology (JAIST)
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Speaker Author-1 
Date Time 2011-09-27 09:25:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2011-33 
Volume (vol) vol.111 
Number (no) no.218 
Page pp.63-68 
Date of Issue 2011-09-19 (RECONF) 

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