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Paper Abstract and Keywords
Presentation 2011-10-20 13:30
Fast Circuit Simulation Based on Improved Latency Insertion Method with Predictor-Corrector Method
Hiroki Kurobe, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.) CAS2011-39 NLP2011-66
Abstract (in Japanese) (See Japanese page) 
(in English) This report describes an improved latency insertion method (LIM) with predictor-corrector method for the fast transient simulation of large networks. The LIM analyzes a network effectively by exploiting latencies in the network. If we have to analyze an ill-constructed circuit, an extremely small value of latency is inserted into the network. However, this treatment leads an extremely small time step size and a large amount of time steps. In order to circumvent this inherent limitation, we propose the predictor-corrector LIM. Our proposed method can employ a large value of latency without incurring the inherent limitation. Thus, the proposed method can perform the fast transient simulation compared with the basic LIM. Finally, an example circuit is analyzed by the conventional methods and the proposed method, we estimate the accuracy and the CPU time of the proposed method.
Keyword (in Japanese) (See Japanese page) 
(in English) fast transient simulation / latency insertion method / predictor-corrector method / tightly coupled transmission lines / / / /  
Reference Info. IEICE Tech. Rep., vol. 111, no. 242, CAS2011-39, pp. 37-42, Oct. 2011.
Paper # CAS2011-39 
Date of Issue 2011-10-13 (CAS, NLP) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CAS2011-39 NLP2011-66

Conference Information
Committee CAS NLP  
Conference Date 2011-10-20 - 2011-10-21 
Place (in Japanese) (See Japanese page) 
Place (in English) Shizuoka Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Circuit and System, etc. 
Paper Information
Registration To CAS 
Conference Code 2011-10-CAS-NLP 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Fast Circuit Simulation Based on Improved Latency Insertion Method with Predictor-Corrector Method 
Sub Title (in English)  
Keyword(1) fast transient simulation  
Keyword(2) latency insertion method  
Keyword(3) predictor-corrector method  
Keyword(4) tightly coupled transmission lines  
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1st Author's Name Hiroki Kurobe  
1st Author's Affiliation Shizuoka University (Shizuoka Univ.)
2nd Author's Name Tadatoshi Sekine  
2nd Author's Affiliation Shizuoka University (Shizuoka Univ.)
3rd Author's Name Hideki Asai  
3rd Author's Affiliation Shizuoka University (Shizuoka Univ.)
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Speaker Author-1 
Date Time 2011-10-20 13:30:00 
Presentation Time 25 minutes 
Registration for CAS 
Paper # CAS2011-39, NLP2011-66 
Volume (vol) vol.111 
Number (no) no.242(CAS), no.243(NLP) 
Page pp.37-42 
#Pages 6 
Date of Issue 2011-10-13 (CAS, NLP) 

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