Paper Abstract and Keywords |
Presentation |
2011-10-21 14:05
[Invited Talk]
Receiver Front-End Design for CMOS High-Speed I/O Masaya Kibune, Hirotaka Tamura, Takuji Yamamoto (FLL) CAS2011-56 NLP2011-83 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A CMOS transceiver macro for wire-line communication is required to operate at higher data rate and to be compatible with wide variety of interface standards, while it needs to be small size and power consumption. This paper introduces the issues of the existing receiver architectures, and shows some techniques to reduce complexity of the digital receiver design to achieve the scalability for both data rate and technology. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
CMOS / High-Speed I/O / Digital Receiver / CDR / Equalization / / / |
Reference Info. |
IEICE Tech. Rep., vol. 111, no. 242, CAS2011-56, pp. 135-140, Oct. 2011. |
Paper # |
CAS2011-56 |
Date of Issue |
2011-10-13 (CAS, NLP) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CAS2011-56 NLP2011-83 |
Conference Information |
Committee |
CAS NLP |
Conference Date |
2011-10-20 - 2011-10-21 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Shizuoka Univ. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Circuit and System, etc. |
Paper Information |
Registration To |
CAS |
Conference Code |
2011-10-CAS-NLP |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Receiver Front-End Design for CMOS High-Speed I/O |
Sub Title (in English) |
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Keyword(1) |
CMOS |
Keyword(2) |
High-Speed I/O |
Keyword(3) |
Digital Receiver |
Keyword(4) |
CDR |
Keyword(5) |
Equalization |
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1st Author's Name |
Masaya Kibune |
1st Author's Affiliation |
FUJITSU LABORATORIES LTD. (FLL) |
2nd Author's Name |
Hirotaka Tamura |
2nd Author's Affiliation |
FUJITSU LABORATORIES LTD. (FLL) |
3rd Author's Name |
Takuji Yamamoto |
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FUJITSU LABORATORIES LTD. (FLL) |
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Speaker |
Author-1 |
Date Time |
2011-10-21 14:05:00 |
Presentation Time |
50 minutes |
Registration for |
CAS |
Paper # |
CAS2011-56, NLP2011-83 |
Volume (vol) |
vol.111 |
Number (no) |
no.242(CAS), no.243(NLP) |
Page |
pp.135-140 |
#Pages |
6 |
Date of Issue |
2011-10-13 (CAS, NLP) |
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