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Paper Abstract and Keywords
Presentation 2011-11-29 09:00
Synthesis of efficient data fetch mechanism from the high level communication description
Masato Minato, Yuki Ando, Seiya Shibata (Nagoya Univ.), Tomoo Kinoshita (Soliton Systems), Shinya Honda, Hiroaki Takada (Nagoya Univ.) VLD2011-67 DC2011-43
Abstract (in Japanese) (See Japanese page) 
(in English) This paper presents efficient data fetch mechanism for the FIFO-based implementation generated by SystemBuilder, a system level design environment. This mechanism achieves speeding up the communication and saving memory cost, and automatically synthesized from the high level communication description with an option. The case study which the data writer and data reader have different active interval shows the efficiency of our method.
Keyword (in Japanese) (See Japanese page) 
(in English) system-level design / DMA / data prefetch / / / / /  
Reference Info. IEICE Tech. Rep., vol. 111, no. 324, VLD2011-67, pp. 91-96, Nov. 2011.
Paper # VLD2011-67 
Date of Issue 2011-11-21 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2011-67 DC2011-43

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2011-11-28 - 2011-11-30 
Place (in Japanese) (See Japanese page) 
Place (in English) NewWelCity Miyazaki 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2010 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2011-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Synthesis of efficient data fetch mechanism from the high level communication description 
Sub Title (in English)  
Keyword(1) system-level design  
Keyword(2) DMA  
Keyword(3) data prefetch  
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1st Author's Name Masato Minato  
1st Author's Affiliation Nagoya University (Nagoya Univ.)
2nd Author's Name Yuki Ando  
2nd Author's Affiliation Nagoya University (Nagoya Univ.)
3rd Author's Name Seiya Shibata  
3rd Author's Affiliation Nagoya University (Nagoya Univ.)
4th Author's Name Tomoo Kinoshita  
4th Author's Affiliation Soliton Systems K.K. (Soliton Systems)
5th Author's Name Shinya Honda  
5th Author's Affiliation Nagoya University (Nagoya Univ.)
6th Author's Name Hiroaki Takada  
6th Author's Affiliation Nagoya University (Nagoya Univ.)
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Speaker Author-1 
Date Time 2011-11-29 09:00:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2011-67, DC2011-43 
Volume (vol) vol.111 
Number (no) no.324(VLD), no.325(DC) 
Page pp.91-96 
#Pages 6 
Date of Issue 2011-11-21 (VLD, DC) 

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