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Paper Abstract and Keywords
Presentation 2011-11-29 13:25
A Scaling Method for a Large FU Array Accerlator on Multiple FPGAs
Kodai Moritaka, Shunsuke Shitaoka, Kazuhiro Yoshimura, Jun Yao, Takashi Nakada, Yasuhiko Nakashima (NAIST) CPSY2011-44
Abstract (in Japanese) (See Japanese page) 
(in English) We proposed previously Linear Array Pipeline Processor (LAPP), which can be used to map an inner
loop of conventional VLIW codes to exploit full parallelism between loop iterations and thus achieve extremely high
per watt performance. However, as it is required to map the whole loop kernel inside the Function Unit (FU) array
in LAPP during acceleration, the allowed length of the loop data
ow graph will be strictly limited by the depth
of the FU array. To address this problem, we propose a method to scale current LAPP towards a large FU array,
based on multi-FPGA architecture in this research. Our implementation result shows that with a hardware increase
of 11.6%, it is possible to distribute the very long loop kernel along the FPGA extending direction. Although the
speed of the connection between FPGAs is currently a bottleneck, our study shows that it is applicable under a
near future FPGA hardware, under the fast development of the on-board serial communication interface.
Keyword (in Japanese) (See Japanese page) 
(in English) multiple FPGAs / multi-gigabit transceiver / FU array / accelerator / / / /  
Reference Info. IEICE Tech. Rep., vol. 111, no. 328, CPSY2011-44, pp. 9-14, Nov. 2011.
Paper # CPSY2011-44 
Date of Issue 2011-11-22 (CPSY) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2011-44

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2011-11-28 - 2011-11-30 
Place (in Japanese) (See Japanese page) 
Place (in English) NewWelCity Miyazaki 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2010 -New Field of VLSI Design- 
Paper Information
Registration To CPSY 
Conference Code 2011-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Scaling Method for a Large FU Array Accerlator on Multiple FPGAs 
Sub Title (in English)  
Keyword(1) multiple FPGAs  
Keyword(2) multi-gigabit transceiver  
Keyword(3) FU array  
Keyword(4) accelerator  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Kodai Moritaka  
1st Author's Affiliation Nara Institute of Science and Technology (NAIST)
2nd Author's Name Shunsuke Shitaoka  
2nd Author's Affiliation Nara Institute of Science and Technology (NAIST)
3rd Author's Name Kazuhiro Yoshimura  
3rd Author's Affiliation Nara Institute of Science and Technology (NAIST)
4th Author's Name Jun Yao  
4th Author's Affiliation Nara Institute of Science and Technology (NAIST)
5th Author's Name Takashi Nakada  
5th Author's Affiliation Nara Institute of Science and Technology (NAIST)
6th Author's Name Yasuhiko Nakashima  
6th Author's Affiliation Nara Institute of Science and Technology (NAIST)
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Speaker Author-1 
Date Time 2011-11-29 13:25:00 
Presentation Time 25 minutes 
Registration for CPSY 
Paper # CPSY2011-44 
Volume (vol) vol.111 
Number (no) no.328 
Page pp.9-14 
#Pages 6 
Date of Issue 2011-11-22 (CPSY) 

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