Paper Abstract and Keywords |
Presentation |
2011-11-29 13:25
An Integer Linear Programming based Multiple Task Allocation Method for Fault Tolerance in Network on Chip Hiroshi Saito (Univ. Aizu), Tomohiro Yoneda (NII), Yuichi Nakamura (NEC) VLD2011-77 DC2011-53 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper proposes a multiple task allocation method for given NoC model, task graph, and the number of expected failure NoC nodes. This method maximizes executable failure patterns for the number of expected
failure NoC nodes. Considering the size of memory and the number of I/O ports, the proposed method statically allocates a task to several NoC nodes based on the integer linear programming (ILP) to obtain the optimum solution. In addition, this paper implements a tool which generates the ILP model. In the experiments, this paper evaluates the number of executable failure patterns and the size of the problem when the communication cost is considered or not. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Network-on-chip / task allocation / failure / integer linear programming / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 111, no. 324, VLD2011-77, pp. 147-152, Nov. 2011. |
Paper # |
VLD2011-77 |
Date of Issue |
2011-11-21 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2011-77 DC2011-53 |
Conference Information |
Committee |
VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
Conference Date |
2011-11-28 - 2011-11-30 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
NewWelCity Miyazaki |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2010 -New Field of VLSI Design- |
Paper Information |
Registration To |
VLD |
Conference Code |
2011-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
An Integer Linear Programming based Multiple Task Allocation Method for Fault Tolerance in Network on Chip |
Sub Title (in English) |
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Keyword(1) |
Network-on-chip |
Keyword(2) |
task allocation |
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failure |
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integer linear programming |
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1st Author's Name |
Hiroshi Saito |
1st Author's Affiliation |
University of Aizu (Univ. Aizu) |
2nd Author's Name |
Tomohiro Yoneda |
2nd Author's Affiliation |
National Institute of Informatics (NII) |
3rd Author's Name |
Yuichi Nakamura |
3rd Author's Affiliation |
NEC System IP Core Research Laboratories (NEC) |
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Speaker |
Author-1 |
Date Time |
2011-11-29 13:25:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2011-77, DC2011-53 |
Volume (vol) |
vol.111 |
Number (no) |
no.324(VLD), no.325(DC) |
Page |
pp.147-152 |
#Pages |
6 |
Date of Issue |
2011-11-21 (VLD, DC) |
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