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Paper Abstract and Keywords
Presentation 2011-11-29 14:40
Implementation of an FU Array Accelerator and its Analysis
Mitsutoshi Saito, Shunsuke Shitaoka, Kazuhiro Yoshimura, Jun Yao, Takashi Nakada, Yasuhiko Nakashima (NAIST) CPM2011-159 ICD2011-91
Abstract (in Japanese) (See Japanese page) 
(in English) We have previously proposed Linear Array Pipeline Processor (LAPP), which can map an inner loop of conventional VLIW codes onto Function Unit (FU) array and use minimum required FUs to exploit performance per watt. In the development of LAPP, we have evaluated logic verifi cation by a software simulation fi rst, and the processor realizability on FPGA. Afterwards, we have evaluated the delay time on ASIC. In this paper, we have evaluated the chip area and clock frequency of ASIC（0.18um CMOS process）from viewpoint of the realizability. The result shows that LAPP implemented with slow process (125 ℃, 1.62V) transistor model can operate at 71.4MHz.
Keyword (in Japanese) (See Japanese page) 
(in English) FU array / processor development environment / ASIC prototyping / / / / /  
Reference Info. IEICE Tech. Rep., vol. 111, no. 327, ICD2011-91, pp. 53-58, Nov. 2011.
Paper # ICD2011-91 
Date of Issue 2011-11-21 (CPM, ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPM2011-159 ICD2011-91

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2011-11-28 - 2011-11-30 
Place (in Japanese) (See Japanese page) 
Place (in English) NewWelCity Miyazaki 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2010 -New Field of VLSI Design- 
Paper Information
Registration To ICD 
Conference Code 2011-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Implementation of an FU Array Accelerator and its Analysis 
Sub Title (in English)  
Keyword(1) FU array  
Keyword(2) processor development environment  
Keyword(3) ASIC prototyping  
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1st Author's Name Mitsutoshi Saito  
1st Author's Affiliation Nara Institute of Science and Technology (NAIST)
2nd Author's Name Shunsuke Shitaoka  
2nd Author's Affiliation Nara Institute of Science and Technology (NAIST)
3rd Author's Name Kazuhiro Yoshimura  
3rd Author's Affiliation Nara Institute of Science and Technology (NAIST)
4th Author's Name Jun Yao  
4th Author's Affiliation Nara Institute of Science and Technology (NAIST)
5th Author's Name Takashi Nakada  
5th Author's Affiliation Nara Institute of Science and Technology (NAIST)
6th Author's Name Yasuhiko Nakashima  
6th Author's Affiliation Nara Institute of Science and Technology (NAIST)
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Speaker Author-1 
Date Time 2011-11-29 14:40:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # CPM2011-159, ICD2011-91 
Volume (vol) vol.111 
Number (no) no.326(CPM), no.327(ICD) 
Page pp.53-58 
#Pages 6 
Date of Issue 2011-11-21 (CPM, ICD) 

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