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Paper Abstract and Keywords
Presentation 2011-12-14 14:40
[Invited Talk] Uniquness Enhancement of PUF Responces Based on the Locations of Random Outputting RS Latches
Dai Yamamoto (Fujitsu Lab.), Kazuo Sakiyama, Mitsugu Iwamoto, Kazuo Ohta (Univ. of Electro-Comm.), Takao Ochiai, Masahiko Takenaka, Kouichi Itoh (Fujitsu Lab.) ISEC2011-68
Abstract (in Japanese) (See Japanese page) 
(in English) Physical Unclonable Functions (PUFs) are expected to represent an important solution for secure ID generation and authentication etc. In general, PUFs are considered to be more secure the larger their output entropy. However, the entropy of conventional PUFs is lower than the output bit length, because some output bits are random numbers, which are regarded as unnecessary for ID generation and discarded. We propose a novel PUF structure based on a Butterfly PUF with multiple RS latches, which generates larger entropy by utilizing location information of the RS latches generating random numbers. More specifically, while conventional PUFs generate binary values (0/1), the proposed PUF generates ternary values (0/1/random) in order to increase entropy. We estimate the entropy of the proposed PUF. According to our experiment with 40 FPGAs, a Butterfly PUF with 128 RS latches can improve entropy from 116 bits to 192.7 bits, this being maximized when the frequency of each ternary value is equal. We also show the appropriate RS latch structure for satisfying this condition, and validate it through an FPGA experiment.
Keyword (in Japanese) (See Japanese page) 
(in English) PUF / Butterfly PUF / RS latch / Random number / FPGA / ID Generation / Authentication /  
Reference Info. IEICE Tech. Rep., vol. 111, no. 337, ISEC2011-68, pp. 29-29, Dec. 2011.
Paper # ISEC2011-68 
Date of Issue 2011-12-07 (ISEC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee ISEC  
Conference Date 2011-12-14 - 2011-12-14 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ISEC 
Conference Code 2011-12-ISEC 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Uniquness Enhancement of PUF Responces Based on the Locations of Random Outputting RS Latches 
Sub Title (in English)  
Keyword(1) PUF  
Keyword(2) Butterfly PUF  
Keyword(3) RS latch  
Keyword(4) Random number  
Keyword(5) FPGA  
Keyword(6) ID Generation  
Keyword(7) Authentication  
Keyword(8)  
1st Author's Name Dai Yamamoto  
1st Author's Affiliation FUJITSU Laboratories Ltd. (Fujitsu Lab.)
2nd Author's Name Kazuo Sakiyama  
2nd Author's Affiliation The University of Electro-Communications (Univ. of Electro-Comm.)
3rd Author's Name Mitsugu Iwamoto  
3rd Author's Affiliation The University of Electro-Communications (Univ. of Electro-Comm.)
4th Author's Name Kazuo Ohta  
4th Author's Affiliation The University of Electro-Communications (Univ. of Electro-Comm.)
5th Author's Name Takao Ochiai  
5th Author's Affiliation FUJITSU Laboratories Ltd. (Fujitsu Lab.)
6th Author's Name Masahiko Takenaka  
6th Author's Affiliation FUJITSU Laboratories Ltd. (Fujitsu Lab.)
7th Author's Name Kouichi Itoh  
7th Author's Affiliation FUJITSU Laboratories Ltd. (Fujitsu Lab.)
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Speaker Author-7 
Date Time 2011-12-14 14:40:00 
Presentation Time 30 minutes 
Registration for ISEC 
Paper # ISEC2011-68 
Volume (vol) vol.111 
Number (no) no.337 
Page p.29 
#Pages 1 
Date of Issue 2011-12-07 (ISEC) 

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