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Paper Abstract and Keywords
Presentation 2011-12-15 16:10
[Poster Presentation] Simulation and Analysis of the Interference Noise between PLL circuits.
Ken Maruhashi, Junki Mizuno, Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino (Osaka Inst. Tech.), Yoshio Matsuda (Kanazawa Univ.) ICD2011-110
Abstract (in Japanese) (See Japanese page) 
(in English) When the multiple PLL circuits are laid out on a single IC chip, the influence of the interference between PLL circuits becomes a critical issue. In order to evaluate the interference noise, we construct a simulation model which consists of the multiple PLL circuits connected each other via substrate, and analyze the phase noise performance by simulation.
Keyword (in Japanese) (See Japanese page) 
(in English) Phase-looked loop circuit (PLL circuit) / Voltage-controlled oscillator (VCO) / Interference Noise / Impulse Sensitivity Function (ISF) / / / /  
Reference Info. IEICE Tech. Rep., vol. 111, no. 352, ICD2011-110, pp. 57-58, Dec. 2011.
Paper # ICD2011-110 
Date of Issue 2011-12-08 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2011-110

Conference Information
Committee ICD  
Conference Date 2011-12-15 - 2011-12-16 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2011-12-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Simulation and Analysis of the Interference Noise between PLL circuits. 
Sub Title (in English)  
Keyword(1) Phase-looked loop circuit (PLL circuit)  
Keyword(2) Voltage-controlled oscillator (VCO)  
Keyword(3) Interference Noise  
Keyword(4) Impulse Sensitivity Function (ISF)  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Ken Maruhashi  
1st Author's Affiliation Osaka Institute of Technology (Osaka Inst. Tech.)
2nd Author's Name Junki Mizuno  
2nd Author's Affiliation Osaka Institute of Technology (Osaka Inst. Tech.)
3rd Author's Name Tsutomu Yoshimura  
3rd Author's Affiliation Osaka Institute of Technology (Osaka Inst. Tech.)
4th Author's Name Shuhei Iwade  
4th Author's Affiliation Osaka Institute of Technology (Osaka Inst. Tech.)
5th Author's Name Hiroshi Makino  
5th Author's Affiliation Osaka Institute of Technology (Osaka Inst. Tech.)
6th Author's Name Yoshio Matsuda  
6th Author's Affiliation Kanazawa University (Kanazawa Univ.)
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Speaker Author-1 
Date Time 2011-12-15 16:10:00 
Presentation Time 110 minutes 
Registration for ICD 
Paper # ICD2011-110 
Volume (vol) vol.111 
Number (no) no.352 
Page pp.57-58 
#Pages 2 
Date of Issue 2011-12-08 (ICD) 

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