Paper Abstract and Keywords |
Presentation |
2012-01-25 13:55
An IPC Control Mechanism for Real-Time Processing on a Prioritized SMT Processor Kensuke Kaneda, Kohei Matsumoto, Nobuyuki Yamasaki (Keio Univ) VLD2011-97 CPSY2011-60 RECONF2011-56 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Although the SMT processor which performs two or more threads simultaneously can improve total throughput, the execution time of each thread varies due to interference between threads, etc. In this paper, we propose a method that controls IPC (Instruction Per Clock Cycle) of threads to maintain their execution speed on a prioritized SMT processor. It also controls the number of instructions executed in each execution cycle of periodic therad for accurate real-time execution. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Real-Time System / SMT / IPC Control / Priority Control / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 111, no. 398, CPSY2011-60, pp. 37-42, Jan. 2012. |
Paper # |
CPSY2011-60 |
Date of Issue |
2012-01-18 (VLD, CPSY, RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
VLD2011-97 CPSY2011-60 RECONF2011-56 |
Conference Information |
Committee |
VLD CPSY RECONF IPSJ-SLDM |
Conference Date |
2012-01-25 - 2012-01-26 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Hiyoshi Campus, Keio University |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
FPGA Applications, etc |
Paper Information |
Registration To |
CPSY |
Conference Code |
2012-01-VLD-CPSY-RECONF-SLDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
An IPC Control Mechanism for Real-Time Processing on a Prioritized SMT Processor |
Sub Title (in English) |
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Keyword(1) |
Real-Time System |
Keyword(2) |
SMT |
Keyword(3) |
IPC Control |
Keyword(4) |
Priority Control |
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1st Author's Name |
Kensuke Kaneda |
1st Author's Affiliation |
Keio University (Keio Univ) |
2nd Author's Name |
Kohei Matsumoto |
2nd Author's Affiliation |
Keio University (Keio Univ) |
3rd Author's Name |
Nobuyuki Yamasaki |
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Keio University (Keio Univ) |
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Speaker |
Author-1 |
Date Time |
2012-01-25 13:55:00 |
Presentation Time |
25 minutes |
Registration for |
CPSY |
Paper # |
VLD2011-97, CPSY2011-60, RECONF2011-56 |
Volume (vol) |
vol.111 |
Number (no) |
no.397(VLD), no.398(CPSY), no.399(RECONF) |
Page |
pp.37-42 |
#Pages |
6 |
Date of Issue |
2012-01-18 (VLD, CPSY, RECONF) |
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