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| Presentation | 2012-03-03 13:00 Development of a FPGA based performance evaluation system for a Ultra-Android prototype Kenji Toda, Osamu Morikawa (AIST), Tomoyuki Morimoto, Michiya Hagimoto, Hiroyuki Uchida, Nobuyuki Hikichi, Yasumori Hibi, Yukoh Matsumoto (Tops Systems)  CPSY2011-91 DC2011-95 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | A performance evaluation system for Ultra-Android platform ,which achieves high performance and less energy consuming android apparatus by using heterogeneous multi-core technology, has developed. The evaluation system is implemented on our originally developed FPGA board and connected with another FPGA board where Ultra-Android runs via AMBA bus. The system is capable of measuring event processing times and response times to pre-defined key-input-sequences. Since software on the microprocessor board is not affected by the measuring and provides precise timing data, performance improvement, in particular real-time performance, is enhanced. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Ultra-Android / FPGA / Performance Evaluation / Heterogeneous Multi-Core / AMB A bus / Real-Time / / | |
| Reference Info. | IEICE Tech. Rep., vol. 111, no. 461, CPSY2011-91, pp. 193-198, March 2012. | |
| Paper # | CPSY2011-91 | |
| Date of Issue | 2012-02-24 (CPSY, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CPSY2011-91 DC2011-95 |
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| Conference Information | |
| Committee | CPSY DC IPSJ-SLDM IPSJ-EMB |
| Conference Date | 2012-03-02 - 2012-03-03 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | CPSY |
| Conference Code | 2012-03-CPSY-DC-SLDM-EMB |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Development of a FPGA based performance evaluation system for a Ultra-Android prototype |
| Sub Title (in English) | |
| Keyword(1) | Ultra-Android |
| Keyword(2) | FPGA |
| Keyword(3) | Performance Evaluation |
| Keyword(4) | Heterogeneous Multi-Core |
| Keyword(5) | AMB A bus |
| Keyword(6) | Real-Time |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Kenji Toda |
| 1st Author's Affiliation | National Institute of Advanced Industrial Science and Technology (AIST) |
| 2nd Author's Name | Osamu Morikawa |
| 2nd Author's Affiliation | National Institute of Advanced Industrial Science and Technology (AIST) |
| 3rd Author's Name | Tomoyuki Morimoto |
| 3rd Author's Affiliation | Tops Systems Corporation (Tops Systems) |
| 4th Author's Name | Michiya Hagimoto |
| 4th Author's Affiliation | Tops Systems Corporation (Tops Systems) |
| 5th Author's Name | Hiroyuki Uchida |
| 5th Author's Affiliation | Tops Systems Corporation (Tops Systems) |
| 6th Author's Name | Nobuyuki Hikichi |
| 6th Author's Affiliation | Tops Systems Corporation (Tops Systems) |
| 7th Author's Name | Yasumori Hibi |
| 7th Author's Affiliation | Tops Systems Corporation (Tops Systems) |
| 8th Author's Name | Yukoh Matsumoto |
| 8th Author's Affiliation | Tops Systems Corporation (Tops Systems) |
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| Speaker | Author-1 |
| Date Time | 2012-03-03 13:00:00 |
| Presentation Time | 30 minutes |
| Registration for | CPSY |
| Paper # | CPSY2011-91, DC2011-95 |
| Volume (vol) | vol.111 |
| Number (no) | no.461(CPSY), no.462(DC) |
| Page | pp.193-198 |
| #Pages | 6 |
| Date of Issue | 2012-02-24 (CPSY, DC) |
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