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Paper Abstract and Keywords
Presentation 2012-03-07 13:45
A GPGPU Implementation of Approximate Regular Expression Matching Algorithm and Comparison with an FPGA Implementation
Yuichiro Utan, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.) VLD2011-139
Abstract (in Japanese) (See Japanese page) 
(in English) Recently, to conduct more advanced approximate string matching, a systolic hardware algorithm for approximate string matching with some regular expression operators and its FPGA implementation have been proposed.
In DNA sequence search, a long pattern and a long text are used.
However, the FPGA implementation cannot handle a long pattern.
This paper proposes a fast matching method for a long pattern on a GPU, which scalably proccesses data.
Also, we evaluate the effectiveness of the GPU implementation comparing with the FPGA implementation.
The experimental results showed that the FPGA and GPU implementations are 8.3 and 2.9 times as fast as a CPU implementation, respectively.
Especially, the GPU implementation is more than 18 times as fast as the CPU implementation when the pattern length is greater than 3200.
Futhermore, the FPGA implementation cannot handle long patterns, because its acceptable pattern length is limited by the size of an FPGA.
Thus, the GPU implementation is effective to deal with a long pattern, such as DNA sequence.
Keyword (in Japanese) (See Japanese page) 
(in English) GPGPU / CUDA / FPGA / String matching / / / /  
Reference Info. IEICE Tech. Rep., vol. 111, no. 450, VLD2011-139, pp. 115-120, March 2012.
Paper # VLD2011-139 
Date of Issue 2012-02-28 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2011-139

Conference Information
Committee VLD  
Conference Date 2012-03-06 - 2012-03-07 
Place (in Japanese) (See Japanese page) 
Place (in English) B-con Plaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Methodologies for System-on-a-chip 
Paper Information
Registration To VLD 
Conference Code 2012-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A GPGPU Implementation of Approximate Regular Expression Matching Algorithm and Comparison with an FPGA Implementation 
Sub Title (in English)  
Keyword(1) GPGPU  
Keyword(2) CUDA  
Keyword(3) FPGA  
Keyword(4) String matching  
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Keyword(6)  
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1st Author's Name Yuichiro Utan  
1st Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
2nd Author's Name Masato Inagi  
2nd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
3rd Author's Name Shinobu Nagayama  
3rd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
4th Author's Name Shin'ichi Wakabayashi  
4th Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
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Speaker Author-1 
Date Time 2012-03-07 13:45:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2011-139 
Volume (vol) vol.111 
Number (no) no.450 
Page pp.115-120 
#Pages 6 
Date of Issue 2012-02-28 (VLD) 

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