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Paper Abstract and Keywords
Presentation 2012-04-24 15:15
Low-Energy Block-Level Instantaneous Comparison 7T SRAM for Dual Modular Redundancy
Yohei Umeki, Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST) ICD2012-16
Abstract (in Japanese) (See Japanese page) 
(in English) This paper proposes a 7T SRAM that realizes a block-level instantaneous comparison feature. The proposed SRAM is useful for operation results comparison in dual modular redundancy (DMR). The data size that can be instantaneously compared is scalable using the proposed structure. The 1-Mb SRAM comprises 16-Kb blocks in which 8-Kb data can be compared in 130.0 ns. The proposed scheme reduces energy consumption in data comparison to 1/418, compared to that of a parallel cyclic redundancy check (CRC) circuit.
Keyword (in Japanese) (See Japanese page) 
(in English) SRAM / 7T bitcell / Comparison circuit / DMR / / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 15, ICD2012-16, pp. 85-90, April 2012.
Paper # ICD2012-16 
Date of Issue 2012-04-16 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2012-16

Conference Information
Committee ICD  
Conference Date 2012-04-23 - 2012-04-24 
Place (in Japanese) (See Japanese page) 
Place (in English) Seion-so, Tsunagi Hot Spring (Iwate) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Memory Device Technologies 
Paper Information
Registration To ICD 
Conference Code 2012-04-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Low-Energy Block-Level Instantaneous Comparison 7T SRAM for Dual Modular Redundancy 
Sub Title (in English)  
Keyword(1) SRAM  
Keyword(2) 7T bitcell  
Keyword(3) Comparison circuit  
Keyword(4) DMR  
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Keyword(6)  
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1st Author's Name Yohei Umeki  
1st Author's Affiliation Kobe University (Kobe Univ.)
2nd Author's Name Shunsuke Okumura  
2nd Author's Affiliation Kobe University (Kobe Univ.)
3rd Author's Name Yohei Nakata  
3rd Author's Affiliation Kobe University (Kobe Univ.)
4th Author's Name Koji Yanagida  
4th Author's Affiliation Kobe University (Kobe Univ.)
5th Author's Name Yuki Kagiyama  
5th Author's Affiliation Kobe University (Kobe Univ.)
6th Author's Name Shusuke Yoshimoto  
6th Author's Affiliation Kobe University (Kobe Univ.)
7th Author's Name Hiroshi Kawaguchi  
7th Author's Affiliation Kobe University (Kobe Univ.)
8th Author's Name Masahiko Yoshimoto  
8th Author's Affiliation Kobe University/JST CREST (Kobe Univ./JST)
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Speaker Author-1 
Date Time 2012-04-24 15:15:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # ICD2012-16 
Volume (vol) vol.112 
Number (no) no.15 
Page pp.85-90 
#Pages 6 
Date of Issue 2012-04-16 (ICD) 

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