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Paper Abstract and Keywords
Presentation 2012-05-31 11:20
Statistical Analysis and its Hardware Implementation on Simulation Results of Systems with Uncertain Inputs
Kosuke Oshima, Shohei Ono, Takeshi Matsumoto, Masahiro Fujita (Univ. of Tokyo) VLD2012-10
Abstract (in Japanese) (See Japanese page) 
(in English) Statistical model checking is a method to analyze systems where variables have some uncertainty. It can be used to check some desired properties are satisfied with some specified probability under such uncertainty. In statistical model checking, the system needs to be simulated and checked for properties, repeatedly. The property checking takes a long time if a property includes many variables and/or a long time range. In this paper, we propose a hardware implementation of BLTL property checkers to accelerate the property checking process. Through the experimental results on Tsunami simulation, we show that the total execution time of statistical model checking can be shorten 30 times compared to a software implementation, by implementing our proposed BLTL property checkers on FPGA.
Keyword (in Japanese) (See Japanese page) 
(in English) statistical model checking / bounded linear temporal logic / FPGA / simulation / / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 71, VLD2012-10, pp. 55-60, May 2012.
Paper # VLD2012-10 
Date of Issue 2012-05-23 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2012-10

Conference Information
Committee IPSJ-SLDM VLD  
Conference Date 2012-05-30 - 2012-05-31 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu International Conference Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System Design, etc. 
Paper Information
Registration To VLD 
Conference Code 2012-05-SLDM-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Statistical Analysis and its Hardware Implementation on Simulation Results of Systems with Uncertain Inputs 
Sub Title (in English)  
Keyword(1) statistical model checking  
Keyword(2) bounded linear temporal logic  
Keyword(3) FPGA  
Keyword(4) simulation  
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1st Author's Name Kosuke Oshima  
1st Author's Affiliation University of Tokyo (Univ. of Tokyo)
2nd Author's Name Shohei Ono  
2nd Author's Affiliation University of Tokyo (Univ. of Tokyo)
3rd Author's Name Takeshi Matsumoto  
3rd Author's Affiliation University of Tokyo (Univ. of Tokyo)
4th Author's Name Masahiro Fujita  
4th Author's Affiliation University of Tokyo (Univ. of Tokyo)
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Speaker Author-1 
Date Time 2012-05-31 11:20:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2012-10 
Volume (vol) vol.112 
Number (no) no.71 
Page pp.55-60 
#Pages 6 
Date of Issue 2012-05-23 (VLD) 

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