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Paper Abstract and Keywords
Presentation 2012-06-22 13:25
A Reduction Technique of Input Sequences for Time-Multiplexed On-Chip Path Delay Measurement Using Embedded Delay Measurement Circuit
Kentaroh Katoh (TNCT) DC2012-10
Abstract (in Japanese) (See Japanese page) 
(in English) Time-multiplexed delay measurement is useful for the reduction of the measurement time of the on-chip delay measurement using embedded delay measurement circuit. However this approach requires extra input sequences for scan shift clock control between measurements and the selection of the end points of the measured paths. These sequences become data overhead. Therefore, the data volume of these extra input sequences should be as small as possible. This paper proposes a reduction technique of the whole input sequences with the reduction of the two input sequences. The volume of input sequence for scan shift clock control between measurements is reduced considering the number of the shift clocks between measurements. The volume of the input sequence for the selection of the end points of the measured paths is reduced by the continuous measurement of the paths with the identical end points. The evaluation shows that the volume of the input sequence for scan shift clock control is 72.6% of the conventional one. The volume of the input sequence for the selection of the end points of the measured paths is 32.2% of the conventional one. The whole input sequence is 82.2% of the conventional one.
Keyword (in Japanese) (See Japanese page) 
(in English) time-multiplexed delay measurement / on-chip delay measurement / input sequence for shift clock control / input sequence for path selection / / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 102, DC2012-10, pp. 7-13, June 2012.
Paper # DC2012-10 
Date of Issue 2012-06-15 (DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2012-06-22 - 2012-06-22 
Place (in Japanese) (See Japanese page) 
Place (in English) Room B3-1 Kikai-Shinko-Kaikan Bldg 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design, Test, Verification 
Paper Information
Registration To DC 
Conference Code 2012-06-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Reduction Technique of Input Sequences for Time-Multiplexed On-Chip Path Delay Measurement Using Embedded Delay Measurement Circuit 
Sub Title (in English)  
Keyword(1) time-multiplexed delay measurement  
Keyword(2) on-chip delay measurement  
Keyword(3) input sequence for shift clock control  
Keyword(4) input sequence for path selection  
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1st Author's Name Kentaroh Katoh  
1st Author's Affiliation Tsuruoka National College of Technology (TNCT)
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Speaker Author-1 
Date Time 2012-06-22 13:25:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2012-10 
Volume (vol) vol.112 
Number (no) no.102 
Page pp.7-13 
#Pages 7 
Date of Issue 2012-06-15 (DC) 

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