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Paper Abstract and Keywords
Presentation 2012-08-30 13:00
Analog Coherent Reception in Super Computer and Data Center Networks
Masataka Ohta (TIT) PN2012-14
Abstract (in Japanese) (See Japanese page) 
(in English) In Supeer Computer and Data Center Networks, where high speed communications are required, there is little signal degradation to be compensated and no frequency difference between transmitters and receivers sharing a local oscillator. Thus, compensation abilities of power consuming digital coherent technology is little useful. Possibilities of analog coherent reception with DLL (Delay Locked Loop) are studied, when phase synchronization is required only for a short term of a packet or a frame.
Keyword (in Japanese) (See Japanese page) 
(in English) Coherent Reception / DLL (Delay Locked Loop) / / / / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 195, PN2012-14, pp. 1-4, Aug. 2012.
Paper # PN2012-14 
Date of Issue 2012-08-23 (PN) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF PN2012-14

Conference Information
Committee PN  
Conference Date 2012-08-30 - 2012-08-31 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitami Institute of Technology 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Photonic network technologies 
Paper Information
Registration To PN 
Conference Code 2012-08-PN 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Analog Coherent Reception in Super Computer and Data Center Networks 
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Keyword(1) Coherent Reception  
Keyword(2) DLL (Delay Locked Loop)  
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1st Author's Name Masataka Ohta  
1st Author's Affiliation Tokyo Institute of Technology (TIT)
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Speaker Author-1 
Date Time 2012-08-30 13:00:00 
Presentation Time 25 minutes 
Registration for PN 
Paper # PN2012-14 
Volume (vol) vol.112 
Number (no) no.195 
Page pp.1-4 
#Pages 4 
Date of Issue 2012-08-23 (PN) 

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