Paper Abstract and Keywords |
Presentation |
2012-11-27 09:25
Rethinking virtual channel usage in network-on-chip Ryosuke Sasakawa, Naoki Fujieda, Shinya Takamaeda-Yamazaki, Kenji Kise (Tokyo Tech) CPSY2012-51 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
An important requirement of routing algorithm is the freedom from deadlock in Network-on-Chip (NoC).For generating deadlock-free routing algorithms, there is a method which divides virtual channels into classes. In this paper, we propose extended methods which additionally provide high performance and utilization of virtual channels. By using cycle-accurate NoC simulator, we conrmed that proposed methods improve performance. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Network on Chip / deadlock avoidance / virtual channel / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 112, no. 322, CPSY2012-51, pp. 21-26, Nov. 2012. |
Paper # |
CPSY2012-51 |
Date of Issue |
2012-11-19 (CPSY) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CPSY2012-51 |
Conference Information |
Committee |
VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
Conference Date |
2012-11-26 - 2012-11-28 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Centennial Hall Kyushu University School of Medicine |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2012 -New Field of VLSI Design- |
Paper Information |
Registration To |
CPSY |
Conference Code |
2012-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Rethinking virtual channel usage in network-on-chip |
Sub Title (in English) |
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Keyword(1) |
Network on Chip |
Keyword(2) |
deadlock avoidance |
Keyword(3) |
virtual channel |
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1st Author's Name |
Ryosuke Sasakawa |
1st Author's Affiliation |
Tokyo Institute of Technology (Tokyo Tech) |
2nd Author's Name |
Naoki Fujieda |
2nd Author's Affiliation |
Tokyo Institute of Technology (Tokyo Tech) |
3rd Author's Name |
Shinya Takamaeda-Yamazaki |
3rd Author's Affiliation |
Tokyo Institute of Technology (Tokyo Tech) |
4th Author's Name |
Kenji Kise |
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Tokyo Institute of Technology (Tokyo Tech) |
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Speaker |
Author-1 |
Date Time |
2012-11-27 09:25:00 |
Presentation Time |
25 minutes |
Registration for |
CPSY |
Paper # |
CPSY2012-51 |
Volume (vol) |
vol.112 |
Number (no) |
no.322 |
Page |
pp.21-26 |
#Pages |
6 |
Date of Issue |
2012-11-19 (CPSY) |