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| Presentation | 2012-12-06 15:00 Performance of Parallel Control Circuit for Benes Networks with Optimized VHDL Description Hiedya Ichimura, Nobuhiro Sato, Yousuke Kato, Hitoshi Obara (Akita Univ.)  CS2012-81 IE2012-95 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | As Internet traffic is skyrocketing, high-performance routers are compelled to scale both their switch size and link speed. The crossbar switch (XBS) has been used in conventional high-performance router, because it allows routers to switch multiple packets in parallel, while its switch control is fairly simple and fast. However, the number of switching elements in XBSs increases as N2, where N is the switch size, and it becomes formidable to implement large-size XBSs. In contrast, Benes switches have a smaller number of switch elements than XBSs, but they require complex switch control to make switching time longer. The aim our study is to realize a fast switch control circuit for Benes switch using parallel control algorithm. Although a prototype of it has been demonstrated in our preliminary work, it suffers from a low operation speed. In this report, we provide a new design of FPGA-based fast parallel switch control circuit. We show through experiments that the new design improved its operation speed by up to 25%. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Benes switch / High performance router / Switch control / Parallel processing / FPGA / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 112, no. 334, CS2012-81, pp. 59-64, Dec. 2012. | |
| Paper # | CS2012-81 | |
| Date of Issue | 2012-11-29 (CS, IE) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CS2012-81 IE2012-95 |
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| Conference Information | |
| Committee | ITE-BCT IPSJ-AVM CS IE |
| Conference Date | 2012-12-06 - 2012-12-07 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Fukuisi-chiiki-kouryu-plaza |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Image Coding, Streaming, etc. |
| Paper Information | |
| Registration To | CS |
| Conference Code | 2012-12-BCT-AVM-CS-IE |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Performance of Parallel Control Circuit for Benes Networks with Optimized VHDL Description |
| Sub Title (in English) | |
| Keyword(1) | Benes switch |
| Keyword(2) | High performance router |
| Keyword(3) | Switch control |
| Keyword(4) | Parallel processing |
| Keyword(5) | FPGA |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Hiedya Ichimura |
| 1st Author's Affiliation | Akita University (Akita Univ.) |
| 2nd Author's Name | Nobuhiro Sato |
| 2nd Author's Affiliation | Akita University (Akita Univ.) |
| 3rd Author's Name | Yousuke Kato |
| 3rd Author's Affiliation | Akita University (Akita Univ.) |
| 4th Author's Name | Hitoshi Obara |
| 4th Author's Affiliation | Akita University (Akita Univ.) |
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| Speaker | Author-1 |
| Date Time | 2012-12-06 15:00:00 |
| Presentation Time | 20 minutes |
| Registration for | CS |
| Paper # | CS2012-81, IE2012-95 |
| Volume (vol) | vol.112 |
| Number (no) | no.334(CS), no.335(IE) |
| Page | pp.59-64 |
| #Pages | 6 |
| Date of Issue | 2012-11-29 (CS, IE) |
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