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Paper Abstract and Keywords
Presentation 2012-12-14 10:45
A Study of FPGA implementation of TV Filter
Ryoutarou Narusawa, Sho Miura, Hiroyuki Tsuji, Tomoaki Kimura (KAIT) SIS2012-42
Abstract (in Japanese) (See Japanese page) 
(in English) "A Study on FPGA implementation of TV Filter"

The Total Variation (TV) filter, a the nonlinear filter that requires iterative process, achieves an excellent performance in the restoration of images degraded by Gaussian noise. In this report, we propose a hardware implementation of TV filter using FPGA, and examine our hardware design of TV filter.
We implemented this hardware to Arria-II GX FPGA, and as a result, the logical block's usage rate was 30%, and the multiplier block's usage rate was 47%. Furthermore, we verified operation of this hardware, and it turns out that the error with software process was less than 5%. In future work, we will implement hardware including memory management and the iteration process of TV Filter.
Keyword (in Japanese) (See Japanese page) 
(in English) TV Filter / FPGA / Hardware Implementation / / / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 348, SIS2012-42, pp. 69-74, Dec. 2012.
Paper # SIS2012-42 
Date of Issue 2012-12-06 (SIS) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee SIS  
Conference Date 2012-12-13 - 2012-12-14 
Place (in Japanese) (See Japanese page) 
Place (in English) Nihon University Tsudanuma Campus 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To SIS 
Conference Code 2012-12-SIS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Study of FPGA implementation of TV Filter 
Sub Title (in English)  
Keyword(1) TV Filter  
Keyword(2) FPGA  
Keyword(3) Hardware Implementation  
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1st Author's Name Ryoutarou Narusawa  
1st Author's Affiliation Kanagawa Institute of Technology (KAIT)
2nd Author's Name Sho Miura  
2nd Author's Affiliation Kanagawa Institute of Technology (KAIT)
3rd Author's Name Hiroyuki Tsuji  
3rd Author's Affiliation Kanagawa Institute of Technology (KAIT)
4th Author's Name Tomoaki Kimura  
4th Author's Affiliation Kanagawa Institute of Technology (KAIT)
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Speaker Author-1 
Date Time 2012-12-14 10:45:00 
Presentation Time 20 minutes 
Registration for SIS 
Paper # SIS2012-42 
Volume (vol) vol.112 
Number (no) no.348 
Page pp.69-74 
#Pages 6 
Date of Issue 2012-12-06 (SIS) 

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