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Paper Abstract and Keywords
Presentation 2013-01-16 11:00
An Architecture for IPv6 Lookup Using Parallel Index Generation Units
Hiroki Nakahara (Kaoghima Univ.), Tsutomu Sasao, Munehiro Matsuura (KIT) VLD2012-111 CPSY2012-60 RECONF2012-65
Abstract (in Japanese) (See Japanese page) 
(in English) This paper shows an area-efficiency and high-performance
architecture for the IPv6 lookup using parallel index generation units~(IGUs)
and a priority encoder.
To reduce the size of memory for the IGU, we adopt a liner transform
and a row-shift decomposition.
Also, this paper shows a design method for parallel IGUs with given prefixes.
Experimental shows that, as for the normalized area and lookup speed,
our architecture outperforms existing FPGA realizations.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / IPv6 / Prefix lookup / Pattern Matching / LPM / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 377, RECONF2012-65, pp. 25-30, Jan. 2013.
Paper # RECONF2012-65 
Date of Issue 2013-01-09 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2012-111 CPSY2012-60 RECONF2012-65

Conference Information
Committee CPSY VLD RECONF IPSJ-SLDM  
Conference Date 2013-01-16 - 2013-01-17 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To RECONF 
Conference Code 2013-01-CPSY-VLD-RECONF-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An Architecture for IPv6 Lookup Using Parallel Index Generation Units 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) IPv6  
Keyword(3) Prefix lookup  
Keyword(4) Pattern Matching  
Keyword(5) LPM  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Hiroki Nakahara  
1st Author's Affiliation Kaoghima University (Kaoghima Univ.)
2nd Author's Name Tsutomu Sasao  
2nd Author's Affiliation Kyushu Institute of Technology (KIT)
3rd Author's Name Munehiro Matsuura  
3rd Author's Affiliation Kyushu Institute of Technology (KIT)
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Speaker Author-1 
Date Time 2013-01-16 11:00:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2012-111, CPSY2012-60, RECONF2012-65 
Volume (vol) vol.112 
Number (no) no.375(VLD), no.376(CPSY), no.377(RECONF) 
Page pp.25-30 
#Pages
Date of Issue 2013-01-09 (VLD, CPSY, RECONF) 


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