Paper Abstract and Keywords |
Presentation |
2013-01-16 14:10
Optimal Design and Performance Evaluation of Residue Arithmetic Circuits with a Binary Coding of Signed-Digit Number Takuya Kobayashi, Kazuhiro Motegi, Shugang Wei (Gunma Univ.) VLD2012-114 CPSY2012-63 RECONF2012-68 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Signed-Digit (SD) has a redundancy by using \{-1,0,1\}.
By applying the redundant binary representation to arithmetic circuits, arithmetic operations provide high performance.
In order to use the SD number into the arithmetic circuits, binary coding for the SD number is necessary.
Combinations of the binary code have a great influence on the performance of arithmetic circuits.
In this paper, we consider the most optimal mapping of the binary code to the SD number for arithmetic circuits.
From the experimental results, we have the most optimal combination of binary code for the modular SD adders and multipliers . |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Signed-Digit(SD) number / residue number system / SD modulo addition / SD modulo multiplication / Binary coding / / / |
Reference Info. |
IEICE Tech. Rep., vol. 112, no. 375, VLD2012-114, pp. 39-44, Jan. 2013. |
Paper # |
VLD2012-114 |
Date of Issue |
2013-01-09 (VLD, CPSY, RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2012-114 CPSY2012-63 RECONF2012-68 |
Conference Information |
Committee |
CPSY VLD RECONF IPSJ-SLDM |
Conference Date |
2013-01-16 - 2013-01-17 |
Place (in Japanese) |
(See Japanese page) |
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(See Japanese page) |
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Paper Information |
Registration To |
VLD |
Conference Code |
2013-01-CPSY-VLD-RECONF-SLDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Optimal Design and Performance Evaluation of Residue Arithmetic Circuits with a Binary Coding of Signed-Digit Number |
Sub Title (in English) |
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Keyword(1) |
Signed-Digit(SD) number |
Keyword(2) |
residue number system |
Keyword(3) |
SD modulo addition |
Keyword(4) |
SD modulo multiplication |
Keyword(5) |
Binary coding |
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1st Author's Name |
Takuya Kobayashi |
1st Author's Affiliation |
Gunma University (Gunma Univ.) |
2nd Author's Name |
Kazuhiro Motegi |
2nd Author's Affiliation |
Gunma University (Gunma Univ.) |
3rd Author's Name |
Shugang Wei |
3rd Author's Affiliation |
Gunma University (Gunma Univ.) |
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Speaker |
Author-1 |
Date Time |
2013-01-16 14:10:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2012-114, CPSY2012-63, RECONF2012-68 |
Volume (vol) |
vol.112 |
Number (no) |
no.375(VLD), no.376(CPSY), no.377(RECONF) |
Page |
pp.39-44 |
#Pages |
6 |
Date of Issue |
2013-01-09 (VLD, CPSY, RECONF) |
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