Paper Abstract and Keywords |
Presentation |
2013-01-24 16:40
Hardware Implementation of the Inhibitory Connected Pulse Coupled Neural Network using FPGA Masahiro Yoshihara, Soichiro Ikuno, Hiroaki Kurokawa (Tokyo Univ of Tech) NLP2012-120 NC2012-110 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Image segmentation is one of an image processing. Image segmentation is used object recognition and object detection. Pulse Coupled Neural Network have been utilized for an image segmentation. Image segmentation using PCNN have been studied to object recognition and object detection systems. PCNN had studied to hardware implementation using FPGA so that PCNN is expected to applied embedded systems for object recognition and object detection. Many embedded systems using color image segmentation have been proposed. However, image segmentation using PCNN uses gray scale images. Inhibitory Connected-Pulse Coupled Neural Network(IC-PCNN) has been proposed as an extension of the PCNN model corresponding to the color image processing. Therefore, in this study, We implemented IC-PCNN as an hardware using FPGA. We evaluated to implemented IC-PCNN. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
image segmentation / inhibitory connected pulse coupled neural network / FPGA / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 112, no. 389, NLP2012-120, pp. 93-98, Jan. 2013. |
Paper # |
NLP2012-120 |
Date of Issue |
2013-01-17 (NLP, NC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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NLP2012-120 NC2012-110 |
Conference Information |
Committee |
NC NLP |
Conference Date |
2013-01-24 - 2013-01-25 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Hokkaido University Centennial Memory Hall |
Topics (in Japanese) |
(See Japanese page) |
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Paper Information |
Registration To |
NLP |
Conference Code |
2013-01-NC-NLP |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Hardware Implementation of the Inhibitory Connected Pulse Coupled Neural Network using FPGA |
Sub Title (in English) |
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Keyword(1) |
image segmentation |
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inhibitory connected pulse coupled neural network |
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FPGA |
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1st Author's Name |
Masahiro Yoshihara |
1st Author's Affiliation |
Tokyo University of Technology (Tokyo Univ of Tech) |
2nd Author's Name |
Soichiro Ikuno |
2nd Author's Affiliation |
Tokyo University of Technology (Tokyo Univ of Tech) |
3rd Author's Name |
Hiroaki Kurokawa |
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Tokyo University of Technology (Tokyo Univ of Tech) |
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Speaker |
Author-1 |
Date Time |
2013-01-24 16:40:00 |
Presentation Time |
20 minutes |
Registration for |
NLP |
Paper # |
NLP2012-120, NC2012-110 |
Volume (vol) |
vol.112 |
Number (no) |
no.389(NLP), no.390(NC) |
Page |
pp.93-98 |
#Pages |
6 |
Date of Issue |
2013-01-17 (NLP, NC) |
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